We propose a new scheme for reducing the test application time in accumulator-based test-pattern generation. Within this framework, we reduce the problem of efficiently generating test-patterns to that of finding the shortest Hamiltonian path in an associated directed graph. The resulting scheme exhibits extremely low demand for hardware based on a combination of decoders whose inputs are driven by a very slow external tester. Experimental results on ISCAS benchmarks substantiate the superiority of the proposed scheme over the previously-published test-set embedding approaches for accumulator-based test generation.

This paper presents a novel method of designing embedded checkers for constant weight codes. The design method is based on an operation that maps a binary vector to a vector of half length and half weight. Applied to words of constant weight codes this operation preserves essential properties of these words. The checkers designed with this method have a much smaller size than previously proposed embedded checkers for constant weight codes and sometimes they are even smaller than some of the non-embedded checkers that are designed using a particular method from the literature.

A novel scheme for reducing the test application time in accumulator-based test-pattern generation is presented. The proposed scheme exhibits extremely low demand for hardware. It is based on a decoder whose inputs are driven by a very slow external tester. Experimental results on ISCAS benchmarks substantiate a test-time reduction of 75%-95% when compared to previously published test-set embedding approaches for accumulator-based test generation.

Self-testing m-out-of-n code checkers are often designed using parallel counters. Each code word is partitioned into two parts. The ones of both parts are counted by two parallel counters or similar circuits and the obtained numbers, after a correction if necessary, are evaluated using another checker. In this paper this checker design method is extended such that the obtained checkers achieve the self-testing property under very weak conditions. It is only required that no checker input gets a constant signal and that the code words occur in a random order so that the checkers can be used as embedded checkers. The basic building blocks of the checkers are two identical parallel counters that only consist of full adders of which some have a special architecture. The obtained checkers have in most cases a much smaller hardware size than previously known embedded m-out-of-n code checkers. The proposed design method that works for all m-out-of-n codes is further extended to make the checkers programmable, i.e. the same m-out-of-n code checker can be used for different values of m.

A possible method to design a Borden code checker is to map the Borden code words to words of an AN arithmetic code and to check the obtained words with an appropriate AN code checker. For t equiv 2 we show how this method can be modified such that a Borden code checker achieves the self-testing property under very weak conditions. It is only required that no checker input line gets a constant signal and that the Borden code words occur in a random order, making the proposed checkers very suitable for use as embedded checkers

A novel method for designing t-UED and BUED code checkers is presented. In particular we consider Borden codes for t = 2/sup k/ - 1, Bose and Bose-Lin codes. The design technique for all three checker types is mainly based on averaging weights and check symbol values of the code words. The checkers have a simple and regular structure that does not depend on the set of code words that is provided by the circuit under check. The checkers are very well suited for use as embedded checkers since they are self-testing with respect to single stuck-at faults and almost all combinational faults in a single cell under very weak assumptions. All three checker types can be tested with only 2 or 3 code words.

Code checkers monitor the outputs of a system in order to detect errors as soon as possible. The presented checker designs for m-out-of-n and Berger codes are well suited for use as embedded checkers since under very weak assumptions they are self-testing with respect to all single stuck-at faults and almost all combinational faults in a single cell. They are built from full adders and flip-flops and have a regular structure. The same checker circuit can be employed for m-out-of-n codes with different values of m. Also, the same circuit can be used for different types of Berger codes. The specific code is determined by the initialization of the checker register.

In highly reliable systems, error detecting codes are employed and errors caused by faulty hardware are indicated on-line by code checkers. We present two novel architectures of embedded self-testing checkers for low-cost arithmetic codes, one based on code word generators and adders, the other based on code word accumulators. In these schemes, the code checker receives all possible code words but one, irrespective of the number of different code words that are produced by the circuit under check (CUC). So any code checker can be employed that is self-testing for all or a particular subset of code words, and the structure of the code checker need not be tailored to the set of code words produced by the CUC. The proposed code word generators and accumulators are built from simple standard hardware structures, counters and end-around-carry adders. They can also be utilized in an off-line BIST environment as pattern generators and test response compactors.

In this paper we propose a new self-checking comparator with one periodic output. The comparator can be used as a two-rail checker or as an equality checker. Two different input patterns are sufficient to detect all the faults considered.

Recently a deterministic built-in self-test scheme has been presented based on reseeding of multiple-polynomial linear feedback shift registers. This scheme encodes deterministic test sets at distinctly lower costs than previously known approaches. In this paper it is shown how this scheme can be supported during test pattern generation. The presented ATPG algorithm generates test sets which can be encoded very efficiently. Experiments show that the area required for synthesizing a BIST scheme that encodes these patterns is significantly less than the area needed for storing a compact test set. Furthermore, it is demonstrated that the proposed approach of combining ATPG and BIST synthesis leads to a considerably reduced hardware overhead compared to encoding a conventionally generated test set.

We propose a new scheme for built-in test (BIT) that uses multiple-polynomial linear feedback shift registers (MP-LFSR's). The same MP-LFSR that generates random patterns to cover easy to test faults is loaded with seeds to generate deterministic vectors for difficult to test faults. The seeds are obtained by solving systems of linear equations involving the seed variables for the positions where the test cubes have specified values. We demonstrate that MP-LFSR's produce sequences with significantly reduced probability of linear dependence compared to single polynomial LFSR's. We present a general method to determine the probability of encoding as a function of the number of specified bits in the test cube, the length of the LFSR and the number of polynomials. Theoretical analysis and experiments show that the probability of encoding a test cube with s specified bits in an s-stage LFSR with 16 polynomials is 1-10/sup -6/. We then present the new BIT scheme that allows for an efficient encoding of the entire test set. Here the seeds are grouped according to the polynomial they use and an implicit polynomial identification reduces the number of extra bits per seed to one bit. The paper also shows methods of processing the entire test set consisting of test cubes with varied number of specified bits. Experimental results show the tradeoffs between test data storage and test application time while maintaining complete fault coverage.>

Controllable self-checking (CSC) checkers can be included into concurrent checking schemes where only a subset of code words will be checked for correctness. A CSC checker can have four different working modes, depending on the scheme in which it operates. The checker can work in the system mode as well as in a test mode. In both modes the checker can either perform its usual check function or suppress it, according to a pair of control signals. We present two types of CSC checkers, the OR-type and the XOR-type CSC checker. If a CSC checker does not receive enough code words to be self-checking it can be supported by internal off-line test capability.>

Controllable self-checking (CSC) checkers can be included into concurrent checking schemes where only a subset of code words will be checked for correctness. A CSC checker can have up to four working modes, depending on the scheme in which it operates. The checker can work in the system mode as well as in a test mode. In both modes the checker can either perform its usual check function or suppress it, according to a pair of control signals. The authors present two types of CSC checkers, the OR-type and the XOR-type CSC checker. If a CSC checker does not receive enough code words to be self-checking it can be supported by internal off-line test capability.>