The wireless sensor network (WSN) has been gaining popularity for automation and performance improvement in different IoT-based applications. The resource-constrained nature and operating environment of IoT make the devices highly vulnerable to different attacks. However, the Physically Unclonable Function (PUF) helps to implement secure and lightweight authentication protocols for IoT. In this context, few computation-intensive authentication protocols are found in the literature that have addressed secure IoT communication in WSN. Besides, these protocols depend on the local storage of PUF-CRP, which is susceptible to security attacks. This work proposes a lightweight and secure authentication protocol for the IoT devices in WSN. A PUF and its machine learning (ML)–based soft model is integrated to ensure secure authentication and lightweight computation in WSN. PUF prevents physical attacks while carrying much less hardware fingerprints, and the ML-based PUF provides the desired resiliency against PUF identity-based attacks by eliminating the requirement of CRP-based storage. The proposed mechanism delivers two-way authentication while nullifying the attacks on IoT. The proposed protocol is implemented on Xilinx Artix-7 FPGA and Raspberry Pi for testability and performance evaluation. Experiment results and analysis signify its low-cost computations and lightweight features desired for IoT.

Internet of Things (IoT) is evolving as a ubiquitous technology to thrive human lives with minimal time and effort. The resource-constrained IoT devices operating in an ambient environment with minimal or no safeguards are highly susceptible to physical invasion. The existing protocols suffer from huge computing resources required for cryptographic primitives and bandwidth overhead of high message passing during authentication. In addition, few of them suffer from multiple executions of disparate protocols incurring huge latency. Effective use of lightweight primitives with adequate security also propels to rethink the design of the IoT protocol. In this work, we developed a lightweight authentication and key exchange protocol that aptly suits the resource-constrained environment. The proposed protocol leverages cryptographic XOR, hash function for secure communication, and physically unclonable function (PUF) for unique device-dependent identity generation and lightweight security solution to prevent physical attacks. This standalone protocol can perform device-to-device and device-to-server authentication without incurring additional communication and computation resources, eradicating the need for disparate protocols. Extensive security analysis against adversarial attacks and bad PUF-model-based attacks are formally verified. In addition, a Scyther verification tool is utilized for security validation. Performance analysis advocates the lightweight features of this protocol. A prototype implemented with Xilinx Spartan-3E FPGA and Raspberry Pi for a smart street light monitoring system endorses the proposed protocol’s acceptability and safeguards against different adversarial attacks.

Hardware Trojans (HTs) are small circuits intentionally designed by an adversary for harmful purposes. These types of circuits are extremely difficult to detect. An HT often requires some specific signals to activate, which are almost impossible to discover. For this reason, test generation for side-channel analysis has gained significant attention in recent times and does not require HT activation. Such test generation techniques aim to generate a large amount of switching activity inside the HT circuit, increasing transient current measurement. However, such methods suffer from either long runtime or reliable results. In this work, a test generation technique is proposed based on the relative switching activity of the circuit to overcome the limitations of the existing works. Initially, the proposed technique measures the impact of each input on rare nets individually using random vector simulation. Potent inputs are selected to obtain a new set of test vectors that provide high relative switching inside a circuit. The proposed method is applied on 11 different ISCAS and 3 ITC 99 benchmark circuits. Experimental results endorse the efficacy of the proposed method outperforming traditional Hamming distance-based re-ordering techniques (up to 20×) while requiring a small runtime.

Hardware Trojans (HTs) are malicious manipulations of the standard functionality of an integrated circuit (IC). Sophisticated defense against HT attacks has become the utmost current research endeavor. In particular, the HTs whose operations depend on the rare activation condition are the most critical ones. Among other techniques, logic test by rare net excitation is advocated as one of the viable detection methods due to no extra hardware requirement. However, logic test faces a tremendous challenge of the overhead of testing configuration. This work presents a methodology based on the primary input’s impact over rare nets using transition probability to select the useful test vectors. To generate a test vector, each input’s toggle probability is calculated, which drastically minimizes the search space. The capability of rare-signal generation selects the final list of test vectors. Simulations performed in the presence of different HT triggers on different benchmark circuits, like ISCAS ’85, ISCAS ’89, and ITC ’99, show that the proposed methodology is capable of producing test vectors with significantly improved rare net coverage. Furthermore, compared to an existing technique, the proposed methodology produces average higher rare switching (around 72%) inside a netlist.

The deployment of wireless sensor networks (WSN) in an untended environment and the openness of the wireless channel bring various security threats to WSN. The resource limitations of the sensor nodes make the conventional security systems less attractive for WSN. Moreover, conventional cryptography alone cannot ensure the desired security against the physical attacks on sensor nodes. Physically unclonable function (PUF) is an emerging hardware security primitive that provides low-cost hardware security exploiting the unique inherent randomness of a device. In this article, we have proposed an authentication and key sharing scheme for the WSN integrating Pedersen’s verifiable secret sharing (Pedersen’s VSS) and Shamir’s secret sharing (Shamir’s SS) scheme with PUF which ensure the desired security with low overhead. The security analysis depicts the resilience of the proposed scheme against different active, passive and physical attacks. Also, the performance analysis shows that the proposed scheme possesses low computation, communication and storage overhead. The scheme only needs to store a polynomial number of PUF challenge-response pairs to the user node. The sink or senor nodes do not require storing any secret key. Finally, the comparison with the previous protocols establishes the dominance of the proposed scheme to use in WSN.

Secure authentication of any Internet-of-Things (IoT) device becomes the utmost necessity due to the lack of specifically designed IoT standards and intrinsic vulnerabilities with limited resources and heterogeneous technologies. Despite the suitability of arbiter physically unclonable function (APUF) among other PUF variants for the IoT applications, implementing it on field-programmable gate arrays (FPGAs) is challenging. This work presents the complete characterization of the path changing switch (PCS) 1 based APUF on two different families of FPGA, like Spartan-3E (90 nm CMOS) and Artix-7 (28 nm CMOS). A comprehensive study of the existing tuning concept for programmable delay logic (PDL) based APUF implemented on FPGA is presented, leading to establishment of its practical infeasibility. We investigate the entropy, randomness properties of the PCS based APUF suitable for practical applications, and the effect of temperature variation signifying the adequate tolerance against environmental variation. The XOR composition of PCS based APUF is introduced to boost performance and security. The robustness of the PCS based APUF against machine learning based modeling attack is evaluated, showing similar characteristics as the conventional APUF. Experimental results validate the efficacy of PCS based APUF with a little hardware footprint removing the paucity of lightweight security primitive for IoT.

The extensive application of field-programmable gate array (FPGA) devices in industrial environments makes FPGA testing a significant area of exploration. The application-dependent testing approach ensures better manufacturing yield compared to the manufacturing testing process since it can bypass the faulty parts without disturbing a given user-defined design. The interconnection resources occupy a large area in the FPGA die, and it is highly error-prone due to the presence of a huge number of transistors. Interconnection resources testing play a major role in the reconfigurable hardware testing area. This paper presents an application-dependent testing technique to generate test configurations for interconnects in static RAM (SRAM)-based FPGAs. To generate a test pattern for interconnects, logic block configurations have been modified. This paper addresses stuck-at faults, different types of dominant bridging faults, and feedback bridging faults. Appropriate constraints have been designed using Boolean satisfiability to test the above faults in the interconnects. Simulations performed on ISCAS'89, MCNC, and ITC'99 benchmark circuits mapped on different FPGA architectures show that the proposed approach can obtain a minimum number of test configurations with 100% fault coverage for the above-mentioned faults and is technology independent which enables it to address new emerging architectures in FPGAs.

Physically unclonable function (PUF) is one of the most advocated security primitives which extracts the uncontrollable intrinsic physical property of the fabrication process to generate secret bits for authentication, random number generation and key generation. Ring oscillator (RO) PUF is the widely adopted PUF design to implement in FPGA platform, but it is highly error prone to environmental noise (i.e. temperature and voltage). The configurable RO (CRO) PUF is advocated to resolve this issue without increasing the area overhead. This paper proposes an enhanced CRO framework which uses latch instead of inverter to build an RO. The use of dedicated latch (i.e. available in an FPGA) in place of inverter eliminates the restriction to use odd number of delay units (inverters) in an RO configuration. The proposed design efficiently utilizes the resources found in a configurable logic block (CLB) to increase the number of RO configurations while using the same area. Also, it provides the flexibility to include a latch in an RO configuration which in turns improve the reliability and the security as well. Experimental results on Xilinx Spartan 3E FPGA establish that the proposed design exhibits high stability despite varying environmental conditions without using any error correcting code or post-processing technique.

Reversible logic is emerging as a prospective logic design style for implementing ultra-low-power VLSI circuits. It promises low-power consuming circuits by nullifying the energy dissipation in irreversible logic. On the other hand, as a potential alternative to CMOS technology, Quantum-dot Cellular Automata (QCA) promises energy efficient digital design with high device density and high computing speed. The integration of reversible logic in QCA circuit is expected to be effective in addressing the issue of energy dissipation at nano scale regime. This work targets the design of reversible ALU (arithmetic logic unit) in QCA framework and proposes a new “Reversible QCA” (RQCA). The primary design focus is on optimizing the number of reversible gates, quantum cost and the garbage outputs that are the most important hindrances in realizing reversible logic. Besides optimization, the fault coverage capability of RQCA under missing/additional cell deposition defects is analysed. The scope of reversible logic is further outstretched by introducing a novel DFT (design for testability) architecture around the reversible ALU that reduces testing overhead. The performance of proposed ALU is evaluated, subjected to different faults, and is established to be more effective than the existing ALU.

This work proposes a testable QCA (Quantum-Dot Cellular Automata) logic gate (UQCALG) realizing the universal functions. The design of UQCALG is based on the Coupled Majority Minority (CMVMIN) QCA structure with the target to reduce wire crossings as well as the number of clock cycles required to operate a QCA circuit. The characterization of defects in such design leads to synthesis of a test block, realized with the majority and minority voters, that ensures the desired testability of a circuit. The experimental designs establish that the UQCALG can result in cost effective design of testable QCA logic circuits that may not be possible with conventional ULG (Universal Logic Gate).