Demo Data from VLDB 2026 / reviewers in the wild / expert
William Berrie
dblp:04/1968
· DBLP profile ↗
1ranked-venue papers
0as first author
0since 2021 · last 2006
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Storage systems · 77% Hardware accelerators and domain-specific architectures · 23% |
Topics — the 3 heaviest of 5, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Storage systems › storage reliability
RAID |
0.1 | 1 | 2006 | FPGA based RAID 6 hardware accelerator · FPGA 2006 |
Storage systems › storage reliability › RAID
RAID-6 |
0.1 | 1 | 2006 | FPGA based RAID 6 hardware accelerator · FPGA 2006 |
Storage systems
storage reliability |
0.1 | 1 | 2006 | FPGA based RAID 6 hardware accelerator · FPGA 2006 |
Methods — techniques the papers use, named apart from their topics
hardware RAID controller design · 0.1
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2006 | FPGA based RAID 6 hardware acceleratorabstractHard disk storage capacity has continued to rise whilst at the same time the cost per megabyte continues to fall. This, combined with increased usage of digital storage for documents, photography and video for both home and business use has led to increased need for reliable data storage system. Redundant arrays of inexpensive disks (RAID) have proven to offer the best characteristics for reliable storage. However, to date RAID based systems have been limited by their support for only single disk erasure tolerance.This paper introduces an efficient hardware RAID 6 controller on an FPGA capable offering support for uninterrupted access during double disk erasures and recovery. Michael P. Gilroy, James Irvine 0001, William Berrie |
FPGA | 3 |