VLDB 2026 Research / reviewers in the wild / expert
Gary L. Craig
dblp:04/3327
· DBLP profile ↗
2ranked-venue papers
2as first author
0since 2021 · last 1988
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 2 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 100% |
Topics — the 4 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation › hardware verification and test › design for testability
built-in self-test |
0.0 | 1 | 1988 | Test Scheduling and Control for VLSI Built-In Self-Test · IEEE Trans. Computers 1988 |
Electronic design automation
hardware verification and test |
0.0 | 1 | 1988 | Test Scheduling and Control for VLSI Built-In Self-Test · IEEE Trans. Computers 1988 |
Electronic design automation › hardware verification and test
test scheduling |
0.0 | 1 | 1988 | Test Scheduling and Control for VLSI Built-In Self-Test · IEEE Trans. Computers 1988 |
Electronic design automation › hardware verification and test
VLSI testing |
0.0 | 1 | 1988 | Test Scheduling and Control for VLSI Built-In Self-Test · IEEE Trans. Computers 1988 |
Methods — techniques the papers use, named apart from their topics
scheduling algorithm · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1988 | Test Scheduling and Control for VLSI Built-In Self-TestabstractThe test scheduling problem for equal length and unequal length tests for VLSI circuits using built-in self-test (BIST) has been modeled. A hierarchical model for VLSI circuit testing is introduced. The test resource sharing model from C. Kime and K. Saluja (1982) is employed to exploit the potential parallelism. Based on this model, very efficient suboptimum algorithms are proposed for defining test schedules for both the equal length test and unequal length test cases. For the unequal length test case, three different scheduling disciplines are defined, and scheduling algorithms are given for two of the three cases. Data on algorithm performance are presented. The issue of the control of the test schedule is also addressed, and a number of structures are proposed for implementation of control.> Gary L. Craig, Charles R. Kime, Kewal K. Saluja |
IEEE Trans. Computers | 1 |
| 1985 | Pseudo-Exhaustive Adjacency Testing: A BIST Approach for Stuck-Open Faults
Gary L. Craig, Charles R. Kime |
ITC | 1 |