Large Language Models (LLMs) have achieved remarkable success in Natural Language Processing (NLP) tasks, but their deployment is severely constrained by intensive computation and memory costs. Block Floating-Point (BFP) extends the dynamic range beyond INT with shared exponents, while reducing memory and alignment overhead compared to floating-point formats. However, when bit-widths are further reduced, BFP becomes sensitive to outliers; existing mixed-precision BFP methods largely rely on heuristic settings of mantissa width and block size, and the induced bit-level sparsity has yet to be systematically leveraged in hardware. In this paper, we propose AO-BFP, an adaptive BFP framework for LLM inference. At the algorithm level, we propose an adaptive outlier exponent mapping mechanism combined with mixed-precision exploration driven by layer-wise sensitivity analysis. At the hardware level, we design a reconfigurable bit-serial accelerator with a unified datapath that efficiently leverages BFP-induced bit sparsity. Compared with prior LLM accelerators such as ANT, OliVe, and BitMoD, AO-BFP achieves superior performance while preserving model accuracy, delivering speedups of 1.61×, 1.39×, and 1.11×, respectively.

Recently, resistive switching random access memory (ReRAM)-based hardware accelerators have demonstrated unprecedented performance compared to digital accelerators. However, due to limitations in the manufacturing process and largescale integration, several significant non-ideal effects, including IR-Drop, Stuck-At-Fault, and device noises in real ReRAM-based crossbar arrays, are typically incurred. These non-ideal effects degrade signal integrity and performance, particularly in crossbar structures used for building high-density ReRAMs. Therefore, finding a fast and efficient software solution that can predict the effects of IR-drop without involving expensive hardware is highly desirable. In this work, addressing the main limitations of existing simulation methods, such as slow speed and high resource costs, we propose an efficient analysis of large-scale ReRAM crossbar arrays and the corresponding non-ideal factors based on sparse matrix modeling. We classify non-ideal factors into linear (e.g., IR-drop) and nonlinear categories (e.g., shot noise). For linear factors, super-nodal sparse LU factorizations are used to solve. The array-level results show that compared to SPICE simulation, our method achieves a numerical solution accuracy of 10.15 with 506.8 1253.3× faster and 17.46 42934.3× reduced memory usage. For nonlinear factors, we propose two solutions based on different requirements. In one method, we obtain an approximate initial solution by solving a linear system while disregarding the nonlinear contributions and subsequently apply an extended Anderson acceleration method to solve the nonlinear equation, which is suitable for high-precision solutions. Another method simplifies the nonlinear equation into an equivalent linear form. Theoretical validation confirms the effectiveness of this method, significantly enhancing simulation speed while maintaining accuracy. Moreover, we build a high-precision ReRAM accelerator architecture with real-time compensation. Experimental results demonstrate that the proposed architecture effectively mitigates accuracy loss caused by non-ideal factors.

The advent of Transformers has revolutionized fields such as computer vision and natural language processing. However, their memory-intensive nature creates significant hurdles for conventional computing platforms such as CPUs and GPUs. Processing near-memory (PNM) architecture has arisen as a promising solution to mitigate the memory wall problem. However, efficiently deploying Transformer models on PNM architecture remains a cutting-edge challenge. To address the practical demands of cloud and edge computing, we propose a novel mapping framework called Energon, which aims to facilitate high-throughput inference of encoderbased Transformers on PNM-based neural network (NN) accelerators, catering to both non-latency-sensitive and latencybounded scenarios. Firstly, Energon introduces a novel pipeline parallelism strategy based on an XY-aligned layout, which offers an enhanced flexibility in pipeline layout compared to existing pipeline parallelism approaches, while adapting to the finegrained partitioning scheme tailored for Transformers to achieve efficient mass parallelism. Secondly, Energon formulates the mapping optimization problems using dynamic programming and integer linear programming, respectively, to jointly optimize network partitioning and pipeline layout construction for a globally optimal mapping solution. Experimental results demonstrate that Energon significantly improves the inference throughput of encoder-based Transformers on PNM accelerators, outperforming state-of-the-art mapping frameworks by 1.1× to 2.3×. Under user-defined latency bounds, it enhances the inference throughput by an average of 43% and up to 123%.

Modern power analysis attacks (PAAs) pose a significant threat to hardware security, and reliably securing integrated systems against advanced PAAs has become an essential design target. The fundamental principle of PAA detection lies in identifying voltage drops induced by malicious probe insertion. However, conventional detection methods often suffer from reduced accuracy when voltage information is obscured by noise. To address this limitation, a real-time PAA detection technique is proposed to achieve high detection accuracy even in environments with significant voltage noise. The voltages of power grid nodes are initially acquired through voltage sensors, and the voltage differential between power grid nodes is evaluated by performing multiple voltage comparisons within a time period, which effectively mitigates the noise effects. Then, these differential measurements are processed by a linear support vector machine (SVM) model to identify anomalous voltage drops. To further optimize hardware efficiency, a reinforcement learning-based method is developed to determine sensor deployment, minimizing power and area overheads while maintaining detection accuracy. Experimental validation of our method demonstrates a high detection accuracy of 87.13% for 0.2 Ω resistance insertions, even under severe noise conditions (20% ofVdd).

Large-scale resistive random access memory (ReRAM) crossbar arrays have attracted considerable interest for in-memory computing (IMC) applications due to their high integration density and intrinsic parallelism. To enable systematic exploration of architectural design spaces, accurate modeling and efficient simulation of arrays are crucial. However, as arrays sizes increase, non-ideal effects—such as IR-Drop, I-V nonlinearity, and device noises—significantly degrade computational accuracy and efficiency. Although SPICE-based circuit simulators provide high fidelity, their excessive computational and memory overhead makes them impractical for simulating large-scale arrays under non-ideal conditions. In this article, we propose an efficient and scalable numerical framework for simulating large-scale ReRAM crossbar arrays under various conditions, including ideal behavior, I-V nonlinearity, and device noises, and so on. The proposed methodology integrates Cholesky decomposition with a fast iterative solver to enhance computational efficiency. Experimental results demonstrate that compared with existing solvers, our framework achieves high accuracy while greatly reducing runtime and memory consumption in modeling large-scale ReRAM crossbar arrays. This advantage is particularly evident under ReRAM nonlinearity and IR-Drop effects, achieving an average speedup of 162.9× over HSPICE across array sizes ranging from 128 to 2048. This work facilitates efficient and accurate design space exploration for next-generation ReRAM-based accelerators.

The Rectilinear Steiner Minimum Tree (RSMT) problem is a key issue in the back-end physical design of integrated circuits (ICs), which directly affects the quality of the routing. In this work, we formulate the RSMT problem as a sequential decision problem to develop an Actor-Critic reinforcement learning framework named GoSteiner. We utilize a directed graph representation method called GST for RSMT. Additionally, we introduce the Delaunay triangulation graph (DT) and sequentially construct GST on DT to solve the RSMT problem. An edge-aware graph attention network (EGAT) is designed to effectively encode the DT graph and the GST, while a transformer-based decoder is built to output policy. Furthermore, we propose a heuristic method to break high-degree nets (> 50 degrees). This approach fully leverages the critic’s ability to accurately estimate the wirelength of nets, significantly enhancing the quality and efficiency in high-degree nets construction. Experimental results demonstrate that compared with the exact algorithm GeoSteiner, GoSteiner only introduces ≤ 0.24% wirelength error on the ISPD18/19 benchmarks with million of nets. Meanwhile, the runtime for net within 500 pins is less than 62.37 ms .

Thermal issues are major concerns in integrated circuits (ICs) design. Typically, high temperature induces stress and carrier mobility changes between different materials, causing timing and reliability challenges in chip. In this paper, we propose a thermal-aware placement engine named ThePlace. It consists of an ultra-fast thermal simulation model using Fourier neural operator (FNO) to solve the steady-state heat conduction equation, followed by a force-directed global placement algorithm to co-optimize the peak temperature and wirelength in placements. The experimental results indicate that compared with the wirelength-driven placement approach DREAMPlace, ThePlace method enables significant temperature reduction with subtle variation in wirelength.

Modern power analysis attacks (PAAs) pose significant threats to hardware security, and reliably securing integrated systems against advanced PAAs has become a significant design target in integrated circuits. However, the detection accuracy of most countermeasures to PAAs significantly decreases when power side-channel information is mixed with voltage noise. In this paper, a real-time PAA detection technique is proposed to achieve high detection accuracy even with large voltage noise. The voltage drops of certain power grid (PG) nodes caused by PAA are evaluated by a number of voltage comparisons between PG nodes, which compensate for the effects of voltage noise. These voltage comparison results are analyzed by machine learning algorithms, and a linear support vector machine (SVM) model is selected as the PAA detection model. The PAAs on an IBM benchmarked microprocessor are applied to evaluate the detection accuracy, and our proposed PAA detection method achieves 93.11% accuracy in detecting a resistance of 1 Ω with noise equal to 20% of Vdd. Furthermore, the power and area overheads (evaluated using a 65-nm CMOS process) of this method are reduced by 68% and 75%, respectively, compared to those of the existing machine learning-based PAA detection techniques.

Layout design of analog integrated circuits is a time-consuming manual process with limited automation methods. Recently, advances in machine learning have opened up possibilities for automated design, making it a viable option to improve efficiency. In this paper, we present an innovative and highly effective approach to achieve automated analog circuit placement. We transform the analog placement constraints into multiple task objectives, and apply multi-task neural network learning to perform accurate placement solutions efficiently. Besides, the global position information is utilized to achieve more orderly placement. Due to the computational properties of the network, the method exhibits versatility in accommodating diverse scales of circuit netlists. Moreover, the model is trained through unsupervised learning. Compared to the supervised counterpart using many generated synthetic layout datasets, the proposed approach dramatically reduces the cost of placement data. Experimental results demonstrate that compared to SOTA works, the proposed placement learning method can achieve significant performance gains.

In this paper, we further explore the potential of analog in-memory computing (AiMC) and introduce an innovative artificial intelligence (AI) accelerator architecture named YOCO, featuring three key proposals: (1) YOCO proposes a novel 8-bit in-situ multiply arithmetic (IMA) achieving 123.8 TOPS/W energy-efficiency and 34.9 TOPS throughput through efficient charge-domain computation and time-domain accumulation mechanism. (2) YOCO employs a hybrid ReRAM-SRAM memory structure to balance computational efficiency and storage density. (3) YOCO tailors an IMC-friendly attention computing flow with an efficient pipeline to accelerate the inference of transformer-based AI models. Compared to three SOTA baselines, YOCO on average improves energy efficiency by up to $3.9 \times \sim 19.9 \times$ and throughput by up to $6.8 \times \sim 33.6 \times$ across $10 \mathrm{CNN} /$ transformer models.

RowHammer poses a serious reliability challenge to modern DRAM systems. As technology scales down, DRAM resistance to RowHammer has decreased by 30× over the past decade, causing an increasing number of benign applications to suffer from this issue. However, existing defense mechanisms have three limitations: 1) they rely on inefficient mitigation techniques, such as time-consuming victim row refresh; 2) they do not reduce the number of effective RowHammer attacks, leading to frequent mitigations; and 3) they fail to recognize that frequently accessed data is not only a root cause of RowHammer but also presents an opportunity for performance optimization.In this paper, we observe that frequently accessed hot data plays a distinct role in security and efficiency: it can induce RowHammer by interfering with adjacent cold data, while also being performance-critical due to its frequent accesses. To this end, we propose Data Isolation via In-DRAM Cache (DIVIDE), a novel defense mechanism that leverages in-DRAM cache to isolate and exploit hot data. DIVIDE offers three key benefits: 1) It reduces the number of effective RowHammer attacks, as hot data in the cache cannot interfere with each other. 2) It provides a simple yet effective mitigation measure by isolating hot data from cold data. 3) It caches frequently accessed hot data, improving average access latency. DIVIDE employs a two-level protection structure: the first level mitigates RowHammer in cache arrays with high efficiency, while the second level addresses the remaining threats in normal arrays to ensure complete protection. Owing to the high in-DRAM cache hit rate, DIVIDE efficiently mitigates RowHammer while preserving both the performance and energy efficiency of the in-DRAM cache. At a RowHammer threshold of 128, DIVIDE with probabilistic mitigation achieves an average performance improvement of 19.6% and energy savings of 20.4% over DDR4 DRAM for fourcore workloads. Compared to an unprotected in-DRAM cache DRAM, DIVIDE incurs only a 2.1% performance overhead while requiring just a modest 1KB per-channel CAM in the memory controller, with no modification to the DRAM chip.

The advent of Transformers has revolutionized computer vision, offering a powerful alternative to convolutional neural networks (CNNs), especially with the local attention mechanism that excels at capturing local structures within the input and achieve state-of-the-art performance. Processing in-memory (PIM) architecture offers extensive parallelism, low data movement costs, and scalable memory bandwidth, making it a promising solution to accelerate Transformer with memory-intensive operations. However, the crucial issue lies in efficiently deploying an entire model onto resource-limited PIM system while parallelizing each transformer block with potentially many computational branches based on local-attention mechanisms. We present Allspark, which focuses on workload orchestration for visual Transformers on PIM systems, aiming at minimizing inference latency. Firstly, to fully utilize the massive parallelism of PIM, Allspark employs a fine-grained partitioning scheme for computational branches, and formats a systematic layout and interleaved dataflow with maximized data locality and reduced data movement. Secondly, Allspark formulates the scheduling of the complete model on a resource-limited distributed PIM system as an integer linear programming (ILP) problem. Thirdly, as local-global data interactions exhibit complex yet regular dependencies, Allspark provides a two-stage placement method, which simplifies the challenging placement of computational branches on the PIM system into the structured layout and greedy-based binding, to minimize NoC communication costs. Extensive experiments on 3D-stacked DRAM-based PIM systems show that Allspark brings$1.2\times$$\sim$$24.0\times$inference speedup for various visual Transformers over baselines. Compared to Nvidia V100 GPU, Allspark-enriched PIM system yields average speedups of$2.3\times$and energy savings of$20\times$$\sim$$55\times$.

Sparse matrix multiplication (SpMM) is widely applied to numerous domains, such as graph processing and machine learning. However, inner product (IP) induces redundant zero-element computing for mismatched nonzero operands, while outer product (OP) lacks input reuse across Process Elements (PEs). Besides, current accelerators only focus on sparse-sparse matrix multiplication (SSMM) or sparse-dense matrix multiplication (SDMM), rarely performing efficiently for both. To compensate for the shortcomings of IP and OP, we propose an inner-outer-hybrid product (IOHP) method, which reuses the input matrix among PEs with IP and removes zero-element calculations with OP in each PE. Based on IOHP, we co-design a accelerator with a unified computing flow, called IOPS, to efficiently process both SSMM and SDMM. It divides the SpMM into three stages: encoding, partial sum (psum) calculation, and address mapping, where the input matrices can be reused among PEs after encoding (IP) and the zero element can be skipped in the latter two stages (OP). Furthermore, an adaptive partition strategy is proposed to tile the input matrices based on their sparsity ratios, effectively utilizing the on-chip storage and reducing DRAM access. Compared with SpArch, we achieve 1.2×~4.3× performance and 1.3×~4.8× energy efficiency, with 1.4×~2.1× DRAM access saving.

Fast and accurate pre-routing timing prediction is crucial in the very-large-scale integration (VLSI) design flow. Existing machine learning (ML)-assisted pre-routing timing evaluators neglect the impact of timing optimization, which may render their approaches impractical in real circuit design flows. To address the challenges posed by timing optimization, we propose PRO-TIME, a pre-routing optimization-aware timing prediction framework that is driven by multimodal learning. Specifically, we propose a novel endpoint embedding framework that integrates both netlist and layout information. A customized graph neural network (GNN) model is used for extracting endpoint-wise netlist information, which is motivated by the delay propagation process. Meanwhile, we apply the U-net model with a masking strategy to extract endpoint-wise layout information. Furthermore, we propose an adaptive layout mask adjustment scheme to boost performance by leveraging the layout information more effectively. Comprehensive experiments on large-scale RISC-V designs with advanced 7-nm technology node demonstrate the superiority of our model compared to the state-of-the-art pre-routing timing evaluators.

The complementary characteristics of visible (VIS) and infrared (IR) modalities play a crucial role in scene perception for autonomous driving, especially under poor lighting conditions. However, effectively leveraging the complementary information from visible and infrared images to further enhance perception performance remains a challenging task. These challenges stem from the difficulty of adaptively balancing the contributions of visible and infrared information under dynamic illumination conditions, the reliance on static fusion strategies that fail to fully utilize cross-modal complementarities, and the limitations of existing datasets in terms of diverse scenes, fine-grained illumination annotations, and high imaging quality. To address the challenges, we propose an Edge-guided Illumination-aware Interactive learning-based Detector (EI2Det). It includes three novel modules. The cross-modal interaction module uses visible-priority and infrared-priority multi-head cross-attention mechanisms to refine inter-modality and intra-modality feature representations, improving the model’s robustness and adaptability. The illumination-aware weighting module predicts illumination intensity levels to dynamically adjust the contributions of visible and infrared features, ensuring effective fusion under various lighting conditions. The edge-guided fusion module leverages critical edge information to guide the detector’s attention to object boundaries, significantly enhancing its localization capability. Additionally, we introduce a Multi-modality Full-time dataset for Autonomous Driving (MFAD), featuring 12,370 image pairs with fine-grained annotations of illumination intensity, covering diverse driving scenarios and weather conditions. Extensive experiments on the public M3FD, KAIST, FLIR, LLVIP, and our MFAD datasets demonstrate superior performance and generalization ability of our approach. The code and dataset will be available athttps://github.com/hukefy/EI2Det.

SRAM-based computing-in-memory (CIM) is an efficient technology for computing neural networks where matrix operations are dominated. However, leveraging sparsity in CIM presents challenges due to the crossbar architecture, which complicates the avoidance of zero element calculations. Previous CIM designs have demonstrated that sparsity can improve energy efficiency, but these approaches often lead to non-negligible accuracy loss or substantial hardware overhead. To address this challenge, we propose a hybrid N:M CIM (HNM-CIM), an algorithm-architecture co-design framework for accelerating Transformers. At the algorithm level, we propose a hybrid N:M pruning (HNMP), a method that combines structured and unstructured sparsity. This approach maintains regularity while preserving the random distributions of sparsity, thereby enhancing model sparsity with negligible accuracy loss and ensuring CIM compatibility. At the hardware level, we introduce a hybrid N:M sparse digital CIM (HNM-CIM) to support HNMP, which can accelerate Transformers with hybrid N:M sparsity patterns. Experimental results show that HNMP can reduce Transformer models by about 3.1× on model size with negligible accuracy loss. Compared with state-of-the-art references, HNM-CIM yields about 2.46× speed up and 1.43× area savings.

A dynamic random access memory (DRAM) relies on periodic refresh operations to prevent data loss caused by charge leakage. As memory capacities continue to grow, refresh power consumption accounts for an increasing proportion of the total DRAM power, and in some contexts, it even becomes a major contributor to power consumption. To address this issue, previous research has explored the tradeoff between DRAM reliability and refresh overhead. However, DRAM reliability degrades as technology nodes advance, making these approaches inapplicable in scenarios, such as servers, where high data reliability is critical. Furthermore, these approaches require modifications to the standard DRAM interface protocol and memory controller (MC), rendering them infeasible for standalone use in computer systems. In this article, we propose an energy-efficient charge-recycling DRAM (CR-DRAM), which enables multiple rounds of charge (i.e., energy) recycling between subarrays within a single autorefresh (AR) process. After refreshing a row, CR-DRAM reuses the charge stored in the bitline (BL) capacitors to supply power for refreshing the next row in another subarray, rather than discharging them directly. Since CR-DRAM is compatible with the joint electron device engineering council (JEDEC) interface standard, it can be easily integrated into modern computer systems. Our circuit-level simulation shows that CR-DRAM significantly reduces AR power consumption by 33.9% compared with conventional DRAM, with a modest area overhead of less than 0.9%. Furthermore, our system-level evaluation shows that CR-DRAM offers an average energy savings of 9.2% (maximum of 11.9%) compared with 8-Gb double data rate 4 (DDR4) DRAM across SPEC-2006 benchmark workloads.

The wafer-on-wafer (WoW) stacked structure exhibits pioneering advantages in near-memory computing but encounters challenges in 3D analysis due to the miniaturization of vertical connection structures and the simplification of vertical drivers. This article introduces a 3D unified analysis method (3D-UAM), which facilitates standard-cell-level signal integrity (SI) analysis across the 3D WoW stacked structure with hybrid processes, including a comprehensive 3D vertical connection theoretical model that bridges the dynamic random access memory (DRAM) and logic netlists. The accuracy of the 3D-UAM is confirmed through consistency analysis with the results of the 3D field model. The authenticity of the 3D-UAM is validated through correlation analysis with the physical test results from the WoW stacked DRAM test chip. The practicality of the 3D-UAM is demonstrated through channel optimization on a 20-layer DRAM WoW structure and power integrity (PI) analysis for the WoW stacked structure.

3D object detection achieves good detection performance in autonomous driving. However, it requires substantial computational resources, which prevents its practical application. 2D object detection has less computational burden but lacks spatial and geometric information embedded in depth. Therefore, we present DALDet, an efficient depth-aware learning based 2D detector, achieving high-performance object detection for autonomous driving. We design an efficient one-stage detection framework and seamlessly integrate depth cues into convolutional neural network by introducing depth-aware convolution and depth-aware average pooling, which effectively improve the detector's ability to perceive 3D space. Moreover, we propose a depth-guided loss function for training DALDet, which effectively improves the localization ability of the detector. Due to the use of depth map, DALDet can also output the distance of the object, which is of great importance for driving applications such as obstacle avoidance. Extensive experiments demonstrate the superiority and efficiency of DALDet. In particular, our DALDet ranks 1st on both KITTI Car and Cyclist 2D detection test leaderboards among all 2D detectors with high efficiency as well as yielding competitive performance among many leading 3D detectors. Code will be available at https://github.com/hukefy/DALDet.

Recently, due to the flexibility and reconfigurability of Coarse-Grained Reconfigurable Architecture (CGRA), CGRA microarchitecture has become an inevitable trend to accelerate the convolution calculation in diverse deep neural networks. However, since the vast microarchitecture design space and the complicated VLSI verification flow, it is a huge challenge to explore a perfect microarchitecture to compromise between multiple performance metrics. In this paper, we formulate the CGRA microarchitecture design as a design space exploration problem, and propose a parallel multi-objective Bayesian optimization framework (PAMBOF) to automatically explore the CGRA microarchitecture design space. Meanwhile, high-precision performance and area models are built to enable fast design space exploration. To approximate the black-box objective function in the design space, the PAMBOF framework first builds multiple Gaussian processes (GP) with deep regularization kernel learning functions (DRKL-GP). Then a parallel Bayesian optimization algorithm is developed to sample a batch of candidate design points, which are simulated in parallel by the performance and area models. Experimental results demonstrate that compared to the prior arts, the proposed PAMBOF framework can search for a CGRA microarchitecture design with the better area and performance in a shorter runtime.

Floorplanning is one of the most critical but time-consuming tasks in the chip design process. Machine learning techniques, especially reinforcement learning, have provided a promising direction for floorplanning design. In this paper, an end-to-end reinforcement learning (RL) framework is proposed to learn a policy for floorplanning automatically, in the combination of edge-augmented graph attention network (EGAT), position-wise multi-layer perceptron, and gated self-attention mechanism. We formulate floorplanning as a Markov Decision Process (MDP) model, where a multi-action mechanism and a dense reward function are developed to adapt the floorplanning problem. In addition, in order to make full use of prior knowledge, we further propose a supervised learning approach on the generated synthetic netlist-floorplan dataset. Experimental results demonstrate that, compared with state-of-the-art floorplanners, the proposed end-to-end framework significantly reduces wirelength with a smaller area.

CNN is indispensable for today’s Artificial Intelligence (AI) applications, but brings dominantly large overhead of data communication. Current works mainly focus on prior off-chip or intuitive/heuristic on-chip access optimization, but with the development of Near Memory Processing (NMP), DRAM access cost has greatly dropped and on&off-chip access optimization needs rethinking as a whole. Thus, this paper proposes a holistic on&off-chip communication-minimized model-architecture acceleration scheme for CNN. First, we derive the layer-wise off-chip communication Lower Bound (LB) based on different data reuse strategies. Second, on-chip LB is derived and overall on&off-chip communication analysis model is presented to provide a solid guidance for on-chip storage allocation, dataflow and architecture design. Finally, we design Window-Primitive (WP) dataflow and a Systolic-Cross-Line (SCL) CNN accelerator based on proposed theoretical model. SCL achieves 3.8 × pJ/MAC energy reduction at 1.4 × less on-chip storage area compared with Eyeriss and 1.3~1.8 × reduction at 3~4 × less area compared with CLB. For NMP, we reduce around 2 × access energy compared with previous systolic NMP architecture.

Feed-forward networks (FFNs) constitute two-thirds of the parameters in a Transformer model and account for over 60% of the computational cost. Recent works have aimed to compress FFNs to reduce the computational and memory overhead during inference. Various methods have been proposed, such as evaluating tokens to implement mixed precision for FFN compression and evaluating input vectors and FFN to compress the parameters. These approaches often require real-time evaluation, sometimes even with specialized hardware architecture for mixed precision. Evaluating inputs with all FFN parameters may also result in significant additional overhead in practical applications. Inspired by the observation of sparse activation in FFNs, we introduce a method called DP-FFN, which can split FFN into several functional partitions, and the computing of FFN is based on these partitions. DP-FFN is a two-stage computation approach: the first is to construct functional partitions by grouping frequently activated neurons, and the second is to conduct fine-grained computations using activated functional partitions to maintain model performance. Experimental results show that DP-FFN achieves 1.71X speedup over a baseline with about 2% accuracy loss while using only 20% of FFN parameters. Compared to a state-of-the-art reference, it achieves 1.4X speedup with almost the same accuracy and the same number of FFN parameters.

DRAM memory is a performance bottleneck for many applications, due to its high access latency. Previous work has mainly focused on data locality, introducing small but fast regions to cache frequently accessed data, thereby reducing the average latency. However, these locality-based designs have three challenges in modern multi-core systems: (1) inter-application interference leads to random memory access traffic, (2) fairness issues prevent the memory controller from over-prioritizing data locality, and (3) write-intensive applications have much lower locality and evict substantial dirty entries. With frequent data movement between the fast in-DRAM cache and slow regular arrays, the overhead induced by moving data may even offset the performance and energy benefits of in-DRAM caching. In this article, we decouple the data movement process into two distinct phases. The first phase is Load-Reduced Destructive Activation (LRDA), which destructively promotes data into the in-DRAM cache. The second phase is Delayed Cycle-Stealing Restoration (DCSR), which restores the original data when the DRAM bank is idle. LRDA decouples the most time-consuming restoration phase from activation, and DCSR hides the restoration latency through prevalent bank-level parallelism. We propose FASA-DRAM, incorporating destructive activation and delayed restoration techniques to enable both in-DRAM caching and proactive latency-hiding mechanisms. Our evaluation shows that FASA-DRAM improves the average performance by 19.9% and reduces average DRAM energy consumption by 18.1% over DDR4 DRAM for four-core workloads, with less than 3.4% extra area overhead. Furthermore, FASA-DRAM outperforms state-of-the-art designs in both performance and energy efficiency.

Bit-serial architectures can handle Neural Networks (NNs) with different weight precision, achieving higher resource efficiency compared with bit-parallel architectures. Besides, the weights contain abundant zero bits owing to the fault tolerance of NNs, indicating that bit sparsity of NNs can be further exploited for performance improvement. However, the irregular proportion of zero bits in each weight causes imbalanced workloads in the Processing Element (PE) array, which degrades performance or induces overhead for sparse processing. Thus, this article proposed a channel-wise bit-sparsity quantization method that keeps the non-zero bit number of each weight in each channel from exceeding a certain threshold and clusters the channels with the same threshold to balance the workloads in PE array with little accuracy loss. Then, we co-designed a sparse bit-serial architecture, called Bit-balance, to improve overall performance, supporting weight-bit sparsity and adaptive bitwidth computation. The whole design was implemented with 65 nm technology at 1 GHz and performs at 447-, 37-, 59-, 240-, and 19-frame/s for AlexNet, VGG-16, ResNet-50, GoogleNet, and Yolo-v3 respectively. Compared with sparse bit-serial accelerator, Bitlet, Bit-balance achieves 1.6$\boldsymbol{\times}$2.1$\boldsymbol{\times}$energy efficiency (frame/J) and 2.3$\boldsymbol{\times}$3.6$\boldsymbol{\times}$resource efficiency (frame/mm${}^{\mathbf{2}}$).

With the widespread use of deep neural networks (DNNs) in intelligent systems, DNN accelerators with high performance and energy efficiency are greatly demanded. As one of the feasible processing-in-memory (PIM) architectures, 3D-stacked-DRAM-based PIM (DRAM-PIM) architecture enables large-capacity memory and low-cost memory access, which is a promising solution for DNN accelerators with better performance and energy efficiency. However, the low-access-cost characteristics of stacked DRAM and the distributed manner of memory access and data storing require us to rebalance the hardware design and DNN mapping. In this paper, we propose NicePIM to efficiently explore the design space of hardware architecture and DNN mapping of DRAM-PIM-based DNN inference accelerators, which consists of three key components: PIM-Tuner, PIM-Mapper and Data-Scheduler. PIM-Tuner optimizes the hardware configurations leveraging a DNN model for classifying area-compliant PIM-node designs and a deep kernel learning model for identifying better hardware parameters. PIM-Mapper explores a variety of DNN mapping configurations, including parallelism between branches of DNN, DNN layer partitioning, DRAM capacity allocation and data layout pattern in DRAM to generate high-hardware-utilization DNN mapping schemes for various hardware configurations. The Data-Scheduler employs an integer-linear-programming-based data scheduling algorithm to alleviate the inter-PIM-node communication overhead of data-sharing brought by DNN layer partitioning. Experimental results demonstrate that NicePIM can optimize hardware configurations for DRAM-PIM systems effectively and can generate high-quality DNN mapping schemes with latency and energy cost reduced by 37% and 28% on average respectively compared to the baseline method.

In recent years, analog circuits have received extensive attention and are widely used in many emerging applications. The high demand for analog circuits necessitates shorter circuit design cycles. To achieve the desired performance and specifications, various geometrical symmetry constraints must be carefully considered during the analog layout process. However, the manual labeling of these constraints by experienced analog engineers is a laborious and time-consuming process. To handle the costly runtime issue, we propose a graph-based learning framework to automatically extract symmetric constraints in analog circuit layout. The proposed framework leverages the connection characteristics of circuits and the devices’ information to learn the general rules of symmetric constraints, which effectively facilitates the extraction of device-level constraints on circuit netlists. The experimental results demonstrate that compared to state-of-the-art symmetric constraint detection approaches, our framework achieves higher accuracy and F$_1$-score.

In recent years, memristive crossbar-based neuromorphic computing systems (NCS) have obtained extremely high performance in neural network acceleration. However, adversarial attacks and conductance variations of memristors bring reliability challenges to NCS design. First, adversarial attacks can fool the neural network and pose a serious threat to security critical applications. However, device variations lead to degradation of the network accuracy. In this article, we propose DFS (Deep neural network Feature importance Sampling) and BFS (Bayesian neural network Feature importance Sampling) training strategies, which consist of Bayesian Neural Network (BNN) prior setting, clustering-based loss function, and feature importance sampling techniques, to simultaneously combat device variation, white-box attack, and black-box attack challenges. Experimental results clearly demonstrate that the proposed training framework can improve the NCS reliability.

In this article, we focus on chip floorplanning, which aims to determine the location and orientation of circuit macros simultaneously, so the chip area and wirelength are minimized. As the highest level of abstraction in hierarchical physical design, floorplanning bridges the gap between the system-level design and the physical synthesis, whose quality directly influences downstream placement and routing. To tackle chip floorplanning, we propose an end-to-end reinforcement learning (RL) methodology with a hindsight experience replay technique. An edge-aware graph attention network (EAGAT) is developed to effectively encode the macro and connection features of the netlist graph. Moreover, we build a hierarchical decoder architecture mainly consisting of transformer and attention pointer mechanism to output floorplan actions. Since the RL agent automatically extracts knowledge about the solution space, the previously learned policy can be quickly transferred to optimize new unseen netlists. Experimental results demonstrate that, compared with state-of-the-art floorplanners, the proposed end-to-end methodology significantly optimizes area and wirelength on public GSRC and MCNC benchmarks.

Graph processing is widely used for many modern applications, such as social networks, recommendation systems, and knowledge graphs. However, processing large-scale graphs on traditional Von Neumann architectures is challenging due to the irregular graph data and memory-bound graph algorithms. Processing-in-memory (PIM) architecture has emerged as a promising approach for accelerating graph processing by enabling computation to be performed directly on memory. Despite having many processing units and high local memory bandwidth, PIM often suffers from insufficient global communication bandwidth and high synchronization overhead due to load imbalance. This article proposes GraphB, a novel PIM-based graph processing system, to address all these issues. From the algorithm perspective, we propose a degree-aware graph partitioning algorithm that can generate balanced partitioning at a low cost. From the architecture perspective, we introduce tile buffers incorporated with an on-chip 2D-Mesh, which provides high bandwidth for inter-node data transfer. Dataflow in GraphB is designed to enable computation–communication overlap and dynamic load balancing. In a PyMTL3-based cycle-accurate simulator with five real-world graphs and three common algorithms, GraphB achieves an average 2.2× and maximum 2.8× speedup compared to the SOTA PIM-based graph processing system GraphQ.

Currently, graph data are particularly common in various fields, and graph algorithms are increasingly widely used. However, due to the features of graph datasets, such as sparsity, the acceleration of graph algorithms with traditional architectures is faced with great challenges. In terms of domain-specific architecture (DSA), accelerators are mostly designed for a specific graph algorithm because of the different features of different graph algorithms. There is still a great need for a general graph algorithmic processing architecture. In this work, we propose a parallel General Graph Processing Architecture, GGPA. As a general graph computing architecture, GGPA can support multiple graph algorithms, realize parallel processing and fully explore the parallelism through a unique and effective subgraph partitioning method. GGPA implements flexibility at the execution paradigm level. During algorithm iteration, GGPA dynamically selects the execution paradigm by analyzing vertex update conditions to achieve the best performance. We verify GGPA at the CPU level and architecture simulator level, and experimental results show that GGPA achieves 1.01x to 5.86x speedup compared to other related start-of-the-art work.

Fast and accurate pre-routing timing prediction is crucial in the very-large-scale integration (VLSI) design flow. Existing machine learning (ML)-assisted pre-routing timing evaluators neglect the impact of timing optimization, which may render their approaches impractical in real circuit design flows. To model the impact of timing optimization, we propose an endpoint embedding framework that integrates netlist-layout information via multimodal fusion. An end-to-end flow is further developed for pre-routing restructure-tolerant prediction on global timing metrics. Comprehensive experiments on large-scale RISC-V designs with advanced 7-nm technology node demonstrate the superiority of our model compared to the SOTA pre-routing timing evaluators.

In recent years, memristive crossbar-based neuromorphic computing systems (NCS) have provided a promising solution to the acceleration of neural networks. However, stuck-at faults (SAFs) in the memristor devices significantly degrade the computing accuracy of NCS. Besides, the memristor suffers from the process variations, causing deviation of the actual programming resistance from its target resistance. In this paper, we propose a reliability-driven design framework for a memristive crossbar-based NCS in combination with general and chip-specific design optimizations. First, we design a general reliability-aware training scheme to enhance the robustness of NCS to SAFs and device variations; a dropconnect-inspired approach is developed to alleviate the impact of SAFs; a new weighted error function, including cross-entropy error (CEE), the$l_{2}$-norm of weights, and the sum of squares of first-order derivatives of CEE with respect to weights, is proposed to obtain a smooth error curve, where the effects of variations are suppressed. Second, given the neural network model generated by the reliability-aware training scheme, we exploit chip-specific mapping and re- training to further improve computation accuracy loss incurred by SAFs. Experimental results show that the proposed method can boost the computation accuracy of NCS and improve the NCS robustness. Note to Practitioners—This work is motivated by the manufacturing reliability problem in a memristive crossbar-based NCS. To enhance the robustness of an NCS to SAFs and device variations, this paper presents a reliability-driven design framework with taking account of both general and chip-specific design optimizations. The experimental results have demonstrated that the proposed framework is superior to the prior arts, and can be easily integrated with existing industrial hardware-based fault tolerance solutions for higher accuracy at lower overhead. Memristive crossbar-based computing system gives hope for the anticipated efficient implementation of artificial neuromorphic networks. With the help of the reliability-driven designs, the computation accuracy is restored, and hence we can expect the wide use of memristive crossbar-based computing system in neuromorphic computing applications.

Some field programmable gate arrays (FPGAs) can be partially dynamically reconfigurable with heterogeneous resources distributed on the chip. FPGA-based partially dynamically reconfigurable system (FPGA-PDRS) can be used to accelerate computing and improve computing flexibility. However, the traditional design of FPGA-PDRS is based on manual design. Implementing the automation of FPGA-PDRS needs to solve the problems of task modules partitioning, scheduling, and floorplanning on heterogeneous resources. Existing works only partly solve problems for the automation process of FPGA-PDRS or model homogeneous resources for FPGA-PDRS. To better solve the problems in the automation process of FPGA-PDRS and narrow the gap between algorithm and application, in this paper, we propose a complete workflow including three parts: pre-processing to generate the lists of task module candidate shapes according to the resource requirements, exploration process to search the solution of task modules partitioning, scheduling, and floorplanning, and post-optimization to improve the floorplan success rate. Experimental results show that, compared with state-of-the-art work, the pre-processing process can reduce the occupied area of task modules by 6% on average; the proposed complete workflow can improve performance by 9.6%, and reduce communication cost by 14.2% with improving the resources reuse rate of the heterogeneous resources on the chip. Based on the solution generated by the exploration process, the post-optimization process can improve the floorplan success rate by 11%.

Partially dynamic reconfiguration (PDR) technology can accelerate the reconfiguration process and overcome hardware resource constraints when facing the challenge of high performance with respect to applications and resources constraints on field-programmable gate arrays (FPGAs). On FPGAs with PDR technology, the available on-chip Block RAM (BRAM) resources may not satisfy the memory requirements for all data. If we reserve more BRAM resources, then the total area of the dynamically reconfigurable region (DRR) that is used for calculation will decrease, with a reduction in system performance. We propose a memory-aware optimization framework to search for the optimal solution considering partitioning, scheduling, and floorplanning, where we make a tradeoff between performance and on-chip memory resources utilization. We then propose methods for memory allocation: An ILP model and a heuristic algorithm are provided to determine the minimum memory requirements and the number of corresponding memory blocks for data, as well as to determine whether the memory block with its stored data is assigned on-chip or off-chip by formulating the problem into a 0-1 knapsack problem and solving it using dynamic programming. Experimental results show that the memory-aware optimization framework and methods of memory allocation can increase the amount of on-chip data access to 29.65% of the total data volume with guaranteed performance.

Convolution neural networks (CNNs) are widely used algorithms in image processing, natural language processing and many other fields. The large amount of memory access of CNNs is one of the major concerns in CNN accelerator designs that influences the performance and energy-efficiency. With fast and low-cost memory access, Processing-In-Memory (PIM) system is a feasible solution to alleviate the memory concern of CNNs. However, the distributed manner of data storing in PIM systems is in conflict with the large amount of data reuse of CNN layers. Nodes of PIM systems may need to share their data with each other before processing a CNN layer, leading to extra communication overhead. In this article, we propose DDAM to map CNNs onto PIM systems with the communication overhead reduced. Firstly, A data transfer strategy is proposed to deal with the data sharing requirement among PIM nodes by formulating a Traveling-Salesman-Problem (TSP). To improve data locality, a dynamic programming algorithm is proposed to partition the CNN and allocate a number of nodes to each part. Finally, an integer linear programming (ILP)-based mapping algorithm is proposed to map the partitioned CNN onto the PIM system. Experimental results show that compared to the baselines, DDAM can get a higher throughput of 2.0× with the energy cost reduced by 37% on average.

Sparsity is an intrinsic property of convolutional neural networks (CNNs), worth exploiting for CNN accelerators. However, the extra processing involved comes with hardware overhead, resulting in only marginal profits for most architectures. Meanwhile, systolic arrays have become increasingly competitive on CNN acceleration for its high spatiotemporal locality and low hardware overhead. However, the irregularity of sparsity induces imbalanced workloads under the rigid systolic dataflow, causing performance degradation. Thus, this article proposed a systolic-array-based architecture, called Sense, for sparse CNN acceleration by model-hardware codesign, enabling large performance gains. To balance input feature map (IFM) and weight loads across the processing element (PE) array, we applied channel clustering to gather IFMs with approximate sparsity for array computation and codesigned a load-balancing weight pruning method to keep the sparsity ratio of each kernel at a certain value with little accuracy loss, improving PE utilization and overall performance. In addition, adaptive dataflow configuration was applied to determine the computing strategy based on the storage ratio of IFMs and weights, lowering$1.17\times $–$1.8\times $dynamic random access memory (DRAM) access compared with Swallow and further reducing system energy consumption. The whole design was implemented on ZynqZCU102 with 200 MHz and performs at 471, 34, 53, and 191 image/s for AlexNet, VGG-16, ResNet-50, and GoogleNet, respectively. Compared with sparse systolic-array-based accelerators, Swallow, fusion-enabled systolic architecture (FESA), and SPOTS, Sense achieves$0.97\times $–$2.18\times $,$1.3\times $–$1.67\times $, and$0.94\times $–$1.82\times $energy efficiency (image/J) on these CNNs, respectively.

In this paper, we propose two separate and lightweight convolutional neural networks, SobelNet and DesNet, which work in parallel, as keypoint detector and descriptor respectively. Sobel filter provides the edge structure map of the grayscale image as the input of SobelNet. The locations of keypoints will be obtained after exerting the non-maximum suppression process on the output score map of SobelNet. Gaussian loss is designed to train SobelNet to detect corner points in the edge structure map as keypoints. In the meantime, a dense descriptor map is produced by DesNet which is trained with Circle loss. Besides, the output score map of SobelNet is utilized while training DesNet. The proposed method is evaluated on two widely used datasets, FM benchmark and ETH benchmark. Compared with other state-ofthe- art methods, SobelNet and DesNet can reduce more than half of the computation and achieve comparable or even better performance. The inference times of an image with the size of 640×480 are 7.59 ms and 1.09 ms for SobelNet and DesNet respectively on RTX 2070 SUPER, which meet the real-time requirement.

Recommendation system is important for internet applications such as Netflix or Tiktok. Collaborative Filtering algorithm is a graph computing algorithm commonly used in recommendation systems. In this paper, we propose an innovative approach called PCFBCD, which stands for Parallel Collaborative Filtering using Block Coordinate Descent to accelerate Collaborative Filtering. First we introduce two new algorithms, Multiple Computation and Permutation (MCP) and Normal Parallel Processing (NPP) that both use BCD method to optimize CF algorithm for higher level parallelism. Based on it we propose a hardware architecture that fully utilize the parallelism. Then we simulate PCFBCD architecture using a general-purpose architecture simulator. Experimental results show that our new approaches achieve 3. 10x to 3. 58x speedup compared to traditional method.

Electronic design automation (EDA) comprises a series of computationally difficult optimization problems that require substantial specialized knowledge as well as a considerable amount of trial-and-error efforts. However, open challenges, including long simulation runtime and lack of generalization, continue to restrict the applications of the existing EDA tools. Recently, learning-based algorithms, especially reinforcement learning (RL), have been successfully applied to handle various combinatorial optimization problems by automatically acquiring knowledge from the past experience. In this article, we formulate the floorplanning problem, the first stage of the physical design flow, as a Markov decision process (MDP). An end-to-end learning-based floorplanning framework GoodFloorplan is proposed to explore the design space, which combines graph convolutional network (GCN) and RL. Experimental results demonstrate that compared with state-of-the-art heuristic-based floorplanners, the proposed GoodFloorplan can provide better area and wirelength.

In three-dimensional integrated circuits (3D-ICs), through silicon via (TSV) is a critical technique in providing vertical connections. However, yield is one of the key obstacles to adopt the TSV-based 3D-ICs technology in the industry. Various fault-tolerance structures using redundant TSVs to repair faulty functional TSVs have been proposed in the literature for yield and reliability enhancement. However, the TSV repair paths under delay constraint cannot always be generated due to the lack of appropriate repair algorithms. In this article, we propose an effective TSV repair strategy for the router-based TSV redundancy architecture, taking into account the delay overhead. First, we prove that the router-based fault-tolerance structure configuration (RFSC) with the delay constraint is equivalent to the length-bounded multicommodity flow (LBMCF) problem. Then, an integer linear programming (ILP) formulation with acceptable scalability is presented to solve the LBMCF problem. The experimental results demonstrate that, compared with state-of-the-art fault-tolerance designs, the proposed ILP model can provide higher yield and lower delay overhead.

In 3-D integrated circuits (3D-ICs), through silicon via (TSV) is a critical technique in providing vertical connections. However, the yield is one of the key obstacles to adopt the TSV-based 3D-ICs technology in industry. Various fault-tolerance structures using redundant TSVs to repair faulty functional TSVs have been proposed in literature for yield and reliability enhancement. But the TSV repair paths under delay constraint cannot always be generated due to the lack of appropriate repair algorithms. In this article, we propose an effective TSV repair strategy for the cellular TSV redundancy architecture, with taking account of the delay overhead. First, we prove that the cellular structure-based fault-tolerance TSV configuration with the delay constraint (CSFTC) is equivalent to the length-bounded multicommodity flow (LBMCF) problem. Next, an integer linear programming formulation is presented to solve the LBMCF problem. Finally, to speed-up the fault-tolerance structure configuration process, an efficient Lagrangian relaxation-based heuristic method is further proposed. Experimental results demonstrate that, compared with the state-of-the-art fault-tolerance structures, the proposed method can provide high yield and low delay overhead.

It is still a grand challenge to implement a high-accuracy and high-performance stereo matching algorithm on a resource-limited hardware platform in stereo vision systems. This paper proposes a resource-efficient pipelined hardware architecture with four-cycle time-sharing for the semi-global matching (SGM) algorithm with weighted path cost aggregation. To save hardware resources, we also combined image down-sampling and disparity skipping in the SGM algorithm. The presented architecture is synthesized and implemented on a Zynq-7 FPGA board, which results in a throughput of${1280 \times 960/62.5}$fps with 75 disparity levels at the maximum frequency of 216 MHz. To improve the accuracy of the disparity map at close range, we also adapt the presented architecture with two-cycle time-sharing, and the disparity range is increased to 128, which attains the processing of${1280 \times 960/116}$fps at 200 MHz on VCU-118 FPGA board; the throughput reaches 18245 MDE/s. The result shows that the whole architecture only takes 50465 LUTs, 48046 Registers, 125.5 BRAMs with 128 disparity levels, which is much more efficient than the latest reference work.

Brain network is a large-scale complex network with scale-free, small-world, and modularity properties, which largely supports this high-efficiency massive system. In this article, we propose to synthesize brain-network-inspired interconnections for large-scale network-on-chips. First, we propose a method to generate brain-network-inspired topologies with limited scale-free and power-law small-world properties, which have a low total link length and extremely low average hop count approximately proportional to the logarithm of the network size. In addition, given the large-scale applications, considering the modularity of the brain-network-inspired topologies, we present an application mapping method, including task mapping and deterministic deadlock-free routing, to minimize the power consumption and hop count. Finally, a cycle-accurate simulator BookSim2 is used to validate the architecture performance with different synthetic traffic patterns and large-scale test cases, including real-world communication networks for the graph processing application. Experiments show that, compared with other topologies and methods, the brain-network-inspired network-on-chips (NoCs) generated by the proposed method present significantly lower average hop count and lower average latency. Especially in graph processing applications with a power-law and tightly coupled inter-core communication, the brain-network-inspired NoC has up to 70% lower average hop count and 75% lower average latency than mesh-based NoCs.

A key factor in reducing power consumption for processors is to improve the accuracy of branch prediction and the optimal use of Branch Target Buffer (BTB) size. The power consumption can be reduced by improving the accuracy of branch prediction if additional increase in power consumption due to prediction logic cannot offset the gain from accurate branch prediction. For applications like Convolutional Neural Networks(CNN), we design a new method called PC-Mix to optimize branch direction prediction and BTB size for reduction of power consumption of RISC-V processors. In simulation, 2.5GHz RISC-V processor design is shown that PC-Mix reduces the power consumption of the original processor on CNN by 35% while keeping performance unchanged or better. Compared with the well-known Gshare mechanism, PC-Mix reduces the total power consumption of CNN by 4% in a worst case scenario. At the same the branch prediction accuracy of our scheme exceeds 95%. Meantime hardware overhead are reduced in the design without affecting performance.

In recent years, memristive crossbar-based neuromorphic computing systems (NCS) have provided a promising solution to the acceleration of neural networks. However, stuck-at faults (SAFs) in the memristor devices significantly degrade the computing accuracy of NCS. Besides, memristors suffer from process variations, causing the deviation of actual programming resistance from its target resistance. In this paper, we propose a novel reliability-driven design framework for a memristive crossbar-based NCS in combination with general and chip-specific design optimizations. First, we design a general reliability-aware training scheme to enhance the robustness of NCS to SAFs and device variations; a dropout-inspired approach is developed to alleviate the impact of SAFs; a new weighted error function, including cross-entropy error (CEE), the l2-norm of weights, and the sum of squares of first-order derivatives of CEE with respect to weights, is proposed to obtain a smooth error curve, where the effects of variations are suppressed. Second, given the neural network model generated by the reliability-aware training scheme, we exploit chip-specific mapping and retraining to further reduce the computation accuracy loss incurred by SAFs. Experimental results clearly demonstrate that the proposed method can boost the computation accuracy of NCS and improve the NCS robustness.

Brain network is a large-scale complex network with scale-free, small-world, and modularity properties, which to a large extent supports this high-efficiency massively parallel computing system known in the world. In this paper, we propose a three-stage method to synthesize a brain-inspired interconnection network for large-scale network-on-chip systems, which minimizes communication hop count, dynamic power consumption, and energy-delay-product. Topology generation, core assignment, and routing path allocation are executed in these three stages, respectively. Experimental results show that our synthesis method can construct large-scale brain-inspired NoC systems with higher communication efficiency and superior performance compared to the state-of-the-art.

Simultaneous Localization and Mapping (SLAM) is considered significant for intelligent mobile robot autonomous pathfinding. Over the past years, many successful SLAM systems have been developed and works satisfactorily in static environments. However, in some dynamic scenes with moving objects, the camera pose estimation error would be unacceptable, or the systems even lose their locations. In this paper, we present SaD-SLAM, a visual SLAM system that, building on ORB-SLAM2, achieves excellent performance in dynamic environments. With the help of semantic and depth information, we find out feature points that belong to movable objects. And we detect whether those feature points are keeping still at the moment. To make the system perform accurately and robustly in dynamic scenes, we use both feature points extracted from static objects and static feature points derived from movable objects to finetune the camera pose estimation. We evaluate our algorithm in TUM RGB-D datasets. The results demonstrate the absolute trajectory accuracy of SaD-SLAM can be improved significantly compared with the original ORB-SLAM2. We also compare our algorithm with DynaSLAM and DS-SLAM, which are designed to fit dynamic scenes.

In recent years, memristive crossbar-based neuromorphic computing systems (NCS) have provided a promising solution to the acceleration of neural networks. However, stuck-at faults (SAFs) in the memristor devices significantly degrade the computing accuracy of NCS. Besides, the memristor suffers from the process variations, causing deviation of the actual programming resistance from its target resistance. In this paper, we propose a reliability-driven network training framework for a memristive crossbar-based NCS, with taking account of both SAFs and device variations challenges. A dropout-inspired approach is first developed to alleviate the impact of SAFs. A new weighted error function, including cross-entropy error (CEE), the l2-norm of weights, and the sum of squares of first-order derivatives of CEE with respect to weights, is further proposed to obtain a smooth error curve, where the effects of variations are suppressed. Experimental results show that the proposed method can boost the computation accuracy of NCS and improve the NCS robustness.

The network-on-chips (NoCs)-based communication architecture is a promising candidate for addressing communication bottlenecks in many-core processors and neural network processors. In this article, we consider the generalized fault-tolerance topology generation problem, where the link (physical channel) or switch failures can happen, for application-specific NoCs (ASNoCs). With a user-defined maximum number of faults, K, we propose an integer linear programming (ILP)-based method to generate ASNoC topologies, which can tolerate at most K faults in switches or links. Given the communication requirements between cores and their floorplan, we first propose a convex-cost-flow-based method to solve a core mapping (CM) problem for building connections between the cores and switches. Second, an ILP-based method is proposed to solve the routing path allocation (PA) problem, where K+1 switch-disjoint routing paths are allocated for every communication flow between the cores. Finally, to reduce switch sizes, we propose to share the switch ports for the connections between the cores and switches and formulate the port sharing problem as a clique-partitioning problem, which is solved by iteratively finding a set of the maximum cliques. Additionally, we propose an ILP-based method to simultaneously solve the CM and routing PA problems when only physical link failures are considered. The experimental results show that the power consumption of fault-tolerance topologies increases almost linearly with K because of the routing path redundancy for fault tolerance. When both switch faults and link faults are considered, port sharing can reduce the average power consumption of fault-tolerance topologies with K = 1, K = 2, and K = 3 by 18.08%, 28.88%, and 34.20%, respectively. When considering only the physical link faults, the experimental results show that compared to the fault-tolerant topology generation (FTTG) algorithm, the proposed method reduces power consumption and hop count by 10.58% and 6.25%, respectively; compared to the de Bruijn Digraph (DBG)-based method, the proposed method reduces power consumption and hop count by 21.72% and 9.35%, respectively.

Confronted with the challenge of high performance for applications and the restriction of hardware resources for field-programmable gate arrays (FPGAs), partial dynamic reconfiguration technology is anticipated to accelerate the reconfiguration process and alleviate the device shortage. In this paper, we propose an integrated optimization framework for task partitioning, scheduling, and floorplanning on partially dynamically reconfigurable FPGAs. The partition, schedule, and floorplan of the tasks are represented by the partitioned sequence triple (PST) (PS, QS, RS), where (PS, QS) is a hybrid nested sequence pair for representing the spatial and temporal partitions, as well as the floorplan, and RS is the partitioned dynamic configuration order of the tasks. The floorplanning and scheduling of task modules can be computed from the P-ST in O(n2) time. To integrate the exploration of the scheduling and floorplanning design space, we use a simulated annealing-based search engine and elaborate a perturbation method, where a randomly chosen task module is removed from the partition sequence triple and then reinserted into a proper position selected from all the O(n3) possible combinations of partition, schedule and floorplan. We also prove a sufficient and necessary condition for the feasibility of the partitioning of tasks and scheduling of task configurations, and derive conditions for the feasibility of the insertion points in a P-ST. The experimental results demonstrate the efficiency and effectiveness of the proposed framework.

In recent years, neuromorphic computing systems based on memristive crossbar have provided a promising solution to enable acceleration of neural networks. However, most of the neural networks used in realistic applications are often sparse. If such sparse neural network is directly implemented on a single memristive crossbar, then it would result in inefficient hardware realizations. In this work, we propose E3D-FNC, an enhanced three-dimesnional (3D) floorplanning framework for neuromorphic computing systems, in which the neuron clustering and the layer assignment are considered interactively. First, in each iteration, hierarchical clustering partitions neurons into a set of clusters under the guidance of the proposed distance metric. The optimal number of clusters is determined by L-method. Then matrix re-ordering is proposed to re-arrange the columns of the weight matrix in each cluster. As a result, the reordered connection matrix can be easily mapped into a set of crossbars with high utilizations. Next, since the clustering results will in turn affect the floorplan, we perform the floorplanning of neurons and crossbars again. All the proposed methodologies are embedded in an iterative framework to improve the quality of NCS design. Finally, a 3D floorplan of neuromorphic computing systems is generated. Experimental results show that E3D-FNC can achieve highly hardware-efficient designs compared to the state of the art.

The semi-global matching algorithm is usually used for generating high-quality and real-time disparity maps in stereo vision systems. To reduce the hardware-resource consumption, we present a multi-stage pipeline hardware architecture with timesharing reuse for semi-global stereo matching. Combined with image down-sampling, jumping disparity, and a post processing, the presented architecture is used in a practical advanced driver-assistance system (ADAS), which is implemented on a Zynq-7 FPGA chip. The whole stereo matching architecture consumes 19,603 LUTs and 61.5 BRAM (36 KB), and the throughput is 2857 Million Disparity Estimation per second (MDE/S), which corresponds to a throughput of 31 fps when processing images with 1280∗960 resolution and 75 disparity levels.

In 3-D integrated circuits (3D-ICs), through silicon via (TSV) is a critical technique in providing vertical connections. However, the yield is one of the key obstacles to adopt the TSV-based 3D-ICs technology in industry. Various fault-tolerance structures using spare TSVs to repair faulty functional TSVs have been proposed in literature for yield and reliability enhancement, but a valid structure cannot always be found due to the lack of effective generation methods for fault-tolerance structures. In this paper, we focus on the problem of adaptive fault-tolerance structure (AFTS) generation. Given the relations between functional TSVs and spare TSVs, we first calculate the maximum number of tolerant faults in each TSV group. Then we propose an integer linear programming-based model to construct the AFTS with minimal multiplexer delay overhead and hardware cost. We further develop a speed-up technique through an efficient min-cost-max-flow model. All the proposed methodologies are embedded in a top-down TSV planning framework to form functional TSV groups and generate AFTSs. Experimental results show that, compared with state-of-the-art, the number of spare TSVs used for fault tolerance can be effectively reduced.

In recent years, neuromorphic computing systems based on memristive crossbar have provided a promising solution to enable acceleration of neural networks. Meanwhile, most of the neural networks used in realistic applications are often sparse. If such sparse neural network is directly implemented on a single memristive crossbar, it would result in inefficient hardware realizations. In this work, we propose 3D-FNC, a 3D floorplanning framework for neuromorphic computing systems in consideration of both crossbar utilization and design cost. 3D-FNC groups neurons that connect more common neurons into one cluster, where the optimal number of clusters is determined by L-method. As a result, the connections of a neural network can be effectively mapped to memristive crossbars or discrete synapses. Finally, a 3D floorplanning for memristive crossbars and neurons is developed to reduce area and wirelength cost. Experimental results show that 3D-FNC can achieve highly hardware-efficient designs, compared to state-of-the-art.

As the most important step of a stereo vision system, stereo matching, which finds the correspondences in stereo image pairs, requires high-quality real-time depth computation. In this paper, a high accuracy and high throughput full-pipeline hardware architecture with disparity and row parallelism is proposed. In the semi-global aggregation stage, to improve the accuracy in discontinuous regions, adaptive weighted path costs are adopted, and, five aggregation paths are used without consuming external memory resources. The proposed hardware architecture is implemented on a Stratix V FPGA, which results in a throughput of 1280×960/197fps with 64 disparity levels at 156MHz.

This paper proposes an integrated optimization framework for task partitioning, scheduling, and floorplanning on partially dynamically reconfigurable FPGAs. In the framework, three problems are represented by a partitioned sequence triple (PS, MS, RS), where (PS, MS) is a hybrid nested sequence pair for floorplanning and RS is a reconfiguration sequence for scheduling. The floorplan and schedule of tasks can be computed from the sequence triple in O(n^2) time. To integrate the exploration of the scheduling and floorplanning design space, a fast perturbation method is elaborated with a simulated annealing-based search engine, where a randomly chosen task is removed from the sequence triple and then inserted back into a proper position selected from all the n^3 possible combinations of partitions, schedule and floorplan. The experimental results demonstrate the efficiency and effectiveness of the proposed framework.

In 3-D integrated circuits (3-D ICs), through silicon via (TSV) is a critical technique to provide vertical connections. However, the yield and reliability challenge of TSV in industry is one of key obstacles to adopt the 3-D ICs technology. Various fault-tolerance structures by using additional spare TSVs (s-TSVs) to repair faulty functional TSVs (f-TSVs) have been proposed in literature for yield and reliability enhancement. However, these structures are formed in standard cell placement stage where all the f-TSVs are already placed. In reality, since the s-TSVs can be only inserted into the whitespace, the quality of the generated repair solution is strongly dependent on the whitespace distribution. In this paper, we propose an efficient TSV planning and repair framework in floorplanning stage, which takes nonuniform TSV distribution and clustered TSV defect-distribution into account. The proposed framework mainly consists of four stages: 1) a whitespace redistribution algorithm that uses a probability-based strategy to make the whitespace distribution more reasonable for the f-TSV planning. Subsequently, a convex-cost flow-based model for f-TSV allocation considering the fault clustering; 2) a top-down globally partitioning combined with a bottom-up locally merging to partition f-TSVs into groups with minimum hardware cost; 3) the min-cost max-flow algorithm for s-TSV allocation with minimum wirelength overhead; and 4) an integer linear programming-based model to form a fault-tolerance structure with minimum multiplexer delay overhead. The experimental results demonstrate that the proposed repair framework can improve the yield with minimum hardware cost and multiplexer delay overhead.

Stereo matching is a key step in stereo vision systems that require high accurate depth information and real-time processing of high definition image streams. This work presents a high-accuracy hardware implementation for the stereo matching based on the guided image filter, which is an edge-preserving filter and simplifies the adaptive support window algorithm. The coefficients in the guided image filter are calculated by the proposed mean filter tree structure, which saves hardware resources by sharing large amounts of additions among filter operations. The reference image is enhanced using Laplacian Filter, which improves the accuracy for the discontinuous disparity regions. Moreover, an 8×8 matching window and customized ping-pong caches are used to improve the whole throughputs. The proposed hardware architecture is implemented on a Cyclone IV FPGA resulting in a throughput of 1080p resolution images at 80fps with high accuracy of disparity.

Application-specific Network-on-Chip (ASNoC) has been proposed as a promising solution to address the global communication challenges in System-on-Chips. However, with the number of cores increasing, the on-chip communication becomes more and more complex and the power consumption imposes the major challenge for designing ASNoCs. In this article, we propose a four-stage floorplanning and topology synthesis approach for ASNoCs with Radio-Frequency Interconnect (RF-I). First, considering the advantage of RF-I in long-distance on-chip communication, we integrate the floorplanning and clustering to explore the proper clustering of cores, where the cores belonging to the same cluster will share the same switch for communications, form an island, and occupy a contiguous physical region. After the switches and network interfaces are inserted into the floorplan, the allocation of routing paths and the RF-I logical channels are integrated in an iterative procedure to generate fine-grained dynamically reconfigurable ASNoC topologies. Finally, considering the signal integrity of RF-I, we adjust the placement of the switches by a simulated annealing-based method to reduce the number of RF-I routing corners. To evaluate the placement of switches, we propose a dynamical programming-based method to route the transmission line with the minimized number of routing corners in linear time. The results show that, using the RF-I, we can reduce the power consumption of ASNoCs by 20% to 26%.

The exponential increase in leakage power and the substantial power-saving opportunities provided by scheduling have made dual-threshold voltage (dual-Vth) an attractive choice for low-leakage-power designs. In this paper, we work under the assumption that functional units (FUs) are allocated after scheduling, and fully explore the solution space of scheduling with dual-Vthoperations to optimize the leakage power of the FUs. First, a binding conflict graph (BCG)-based scheduling method is presented to minimize the number of FUs. Second, the BCG-based method is extended to allow scheduling with dual-Vthoperation targeting the minimization of leakage power. In timing-constrained scheduling, each operation in the data flow is initialized with low-Vth. Then, starting from an operation schedule with the timing constraint satisfied, we scale the sets of low-Vthoperations in the off-critical paths with high-Vthso as to reduce the number of low-VthFUs without increasing the total delay. Finally, a scheduling method for minimizing the leakage power under both timing and resource constraints is presented. The results of benchmark tests show that the proposed algorithms can reduce the leakage power reported in previous works by 10.2% while maintaining high circuit performance.

In this work, we focus on the problem of latency-constrained scheduling with consideration of multiple voltage technologies in High-level synthesis. Without the resource concern, we propose an Integer Linear Programming (ILP) formulation and further relax it to a piecewise Linear Programming (LP) problem, which is optimally solved using the efficient piecewise-linear extended network simplex method(PLNSM). The experimental results showed 80X+ speedup compared to the general LP formulation. Considering the resource usage, we propose a two-stage heuristic Network Simplex Method based Power-efficient Multiple Voltage Scheduling(NPMVS) method. Firstly, the above relaxed LP formulation is modified to perform mobility allocation and delay assignment for the operations so as to minimize the power and the differences between the allocated operation mobilities and the predefined target mobilities. The modified formulation is solved using the PLNSM and iteratively performed to minimize power and resource density variation in control steps by gradually updating the predefined target mobilities. Secondly, with the allocated operation mobilities, we apply dependency-free operation scheduling with the objective of minimizing the resource usage. Experimental results show that the proposed method can produce optimum solutions for all 6 benchmarks with 14 groups of data in a maximum time of 0.25 second.

As technology scaling, three-dimensional integrated circuits (3D-ICs) are emerging as a promising solution to address the challenges in system on chips (SoCs). Moreover, it's a necessity to design an efficient Network-on-Chip (NoC) topology for the interconnection issues of 3D SoCs. In this paper, we propose a topology-aware floorplanning method to determine the power-performance efficient 3D NoC topology. Unlike the previous works which explore the path allocation of the NoC components and Through-Silicon Vias (TSVs) assignment after the floorplan of cores is fixed, we integrate these steps (the clustering of cores + the placement of cores and switches + the path allocation + the TSV-aware topology evaluation) within the 3D floorplanning procedure. Experimental results show the effectiveness of our method.

In this paper, we address the problem of scheduling operations into control steps with dual threshold voltage (dual-Vth) technique under timing and resource constraints. Recently, some scheduling methods are proposed based on the mobility overlap removal, and it is a hard problem to remove the mobility overlap optimally. There might be no feasible solution with an improper mobility overlap removal. In this work, we implement the mobility overlap removal together with dual threshold voltage technique to minimize the total leakage power. A simulated-annealing based method is introduced to explore the optimal solution. For each mobility overlap removal, a probability-based method is proposed to schedule operations at appropriate control steps, and to assign them with proper threshold voltages. The experimental results show the effectiveness of the proposed method.

A multilayer routing system usually adopts multiple interconnect configuration with different wire sizes and thicknesses. Since thicker layers of metal lead to fatter wires with smaller resistance, the layer assignment of nets has a large impact on the interconnect delay. However, such layer dependent characteristics have been ignored by most of the state-of-the-art academic layer assignment methods. To remedy this deficiency, this work studies a more effective layer assignment problem under such multi-tier interconnect structure, which arises during 3D global routing and focuses on minimizing both delays and via count. This work presents a two-stage algorithm to solve the problem, which first minimizes the total delay and via count simultaneously by dynamic programming and negotiation technique, and then further minimizes the maximum delay carefully while not increasing the via count. The experimental results on ICCAD09 benchmarks show that the proposed algorithm can significantly reduce the total delay and maximum delay while still keeping roughly the same via count, compared with the state-of-the-art via count minimization layer assignment method NVM.

We considered the one-sided single-detour untangling twisted nets problem for printed circuit board bus routing. A previous optimal dynamic programming based O(n3) algorithm was proposed in a previous work, where n is the number of nets. In this paper, we propose an optimal O(n) untangling algorithm without considering capacity, and this algorithm is further modified to consider capacity. Experimental results show that our algorithms runs much faster than the previous work due to its low time complexity.

In this paper, we propose a method of floorplanning with voltage island generation for system-on-chips (SoC) designs, which is deeply coupled with voltage island partitioning and voltage assignment, and has a good scalability. Floorplans with voltage islands are represented using nested Sequence Pairs, where the cores involved in the same voltage island consecutively appear in the sequences. Starting from a randomly generated initial floorplan, where each non chip-level core occupies an individual voltage island, we iteratively improve the solution by removing a core from the floorplan, then, inserting back the core by trying all the possible O(n2) block positions, which are defined as the combinations of insertion points and voltage islands. An almost linear algorithm is devised to roughly but quickly filter many worse block positions, in each iteration, considering fixed-outline constraints, wirelength, power, power/ground routing resources, and level shifters. Compared with the latest work, the proposed method shows 9.74% and 21.04% improvements respectively on the wirelength and power when all the blocks are hard. When soft blocks are involved, the proposed method shows 12.38% wirelength reduction and 3.10% more power saving with a penalty of 7.5% whitespace. Moreover, more than 20X speedups can be obtained for the large test cases.

Low power design has become one of the most significant requirements when CMOS technology entered the nanometer era. Therefore, timing budget is often performed to slow down as many components as possible so that timing slacks can be applied to reduce the power consumption while maintaining the performance of the whole design. Retiming is a procedure that involves the relocation of flip-flops (FFs) across logic gates to achieve faster clocking speed. In this paper we show that the retiming and slack budgeting problem can be formulated to a convex cost dual network flow problem. Both the theoretical analysis and experimental results show the efficiency of our approach which can not only reduce power consumption by 8.9%, but also speedup previous work by 500 times.

As technology advances, 3-D stacking of silicon layers is emerging as a promising approach to address the integration challenges faced by current System-on-Chips (SoCs). Designing efficient Network- on-Chips (NoCs) is necessary to handle the 3-D interconnect complexity. In this paper, we present a four-stage synthesis approach to determine the power-performance efficient 3-D NoC topology for the application. First, we propose an algorithm to explore optimal clustering of cores during 3-D floorplanning. Then, an Integer Linear Programming (ILP) algorithm is proposed to place switches and network interfaces on the 3-D floorplan. Thirdly, a power and timing aware path allocation algorithm is carried out to determine the connectivity across different switches. Last, a min-cost max-flow based algorithm is proposed for Through-Silicon Via (TSV) assignment to minimize the link power consumption. Experimental results show the effectiveness of the proposed algorithm.

Network-on-chip (NoC) architectures have been proposed as a promising alternative to classical bus-based communication architectures. In this paper, we propose a two phases framework to solve application-specific NoCs topology generation problem. At floorplanning phase, we carry out partition driven floorplanning. At post-floorplanning phase, a heuristic method and a min-cost max-flow algorithm is used to insert switches and network interfaces. Finally, we allocate paths to minimize power consumption. The experimental results show our algorithm is effective for power saving.

We revisit voltage partitioning problem when the mapped voltages of functional units are predetermined. If energy consumption is estimated by formulation E=CV2,a published work claimed this problem was NP-hard. We clarify that it is polynomial solvable, then propose an optimal algorithm, its time complexity is O(nk+k2d) which is best so far, where n, k, and d are respectively the numbers of functional units, available supply voltages, and voltages employed in the final design. In reality, considering leakage power the energy-voltage curve is not simply monotonically increasing and there is still no optimal polynomal polynomial time algorithm. However, under the assumption that energy-voltage curve is quasiconvex, which is also a good approximation to actual situation, the optimal solution can be got in time O(nk2). Experimental results show that our algorithms are more efficient than previous works.

As technology advances, 3-D ICs can significantly alleviate the interconnect problem coming with the decreasing of feature size and are promising for heterogeneous integration. In 3-D ICs, one of the key challenges is the vertical technology, using through-silicon via (TSV) for different device layers connection. In this paper, by noticing the TSV assignment comes under the influence of the whitespace distribution in a given 3-D floorplan, we proposed an algorithm called whitespace insertion (WSI) based on the floorplan-representation Sequence Pair to make the whitespace distribution in the given floorplan more reasonable for TSV insertion. When given 3-D circuit placement or floorplan results, we also proposed a minimum spanning tree based algorithm for TSV assignment to minimize the total wire length, assuming each net may have at most one TSV on each device layer. Experimental results show that, in the given 3-D floorplans there is a huge gap about 45.54% of the wire length increase between the ideal and the practice. And based on our method, the total wire length can be reduced by 13% on average without changing the chip area.

Power optimization has become a significant issue when the CMOS technology entered the nanometer era. Multiple-Supply Voltage (MSV) is a popular and effective method for power reduction. Level shifters may cause area and Interconnect Length Overhead(ILO), and should be considered during floorplanning and post-floorplanning stages. In this paper, we propose a two phases framework VLSAF to solve voltage and level shifter assignment problem. At floorplanning phase, we use: a convex cost network flow algorithm to assign voltage; a minimum cost flow algorithm to assign level shifter. At post-floorplanning phase, a heuristic method is adopted to redistribute white spaces and calculate the positions and shapes of level shifters. Experimental results show VLSAF is effective.

In this paper, we propose a fixed-outline floorplanning (FOFP) method [insertion-after-remove (IAR) FP]. An elaborated method for perturbing solutions, the IAR, is devised. This perturbation uses a technique of enumerating block positions, which is implemented based on the floorplan-representation sequence pair. The proposed perturbation method can greatly accelerate searching-based algorithms, such as simulated annealing, by skipping many solutions that fail to meet the fixed-outline constraint. Moreover, based on the analysis of the diverse objective functions used in the existing research works, we suggest for the FOFP a new objective function which is still effective when combined with other objectives. Experimental results show that, if area and wirelength are optimized simultaneously, using less time, the proposed method obtains much higher average success rate for the FOFP with various aspect ratios, while the wirelength with the fixed-outline constraint is reduced by 20% on average, compared with the latest fixed-outline floorplanners. On the other hand, we validated once more by experiments that an aspect ratio close to one is beneficial to wirelength, and hence, a larger area weight is necessary for the FOFP with a larger aspect ratio to ensure feasible solutions.

In this paper, we propose a stable fixed-outline floorplanning method(IARFP). An elaborated method for perturbing solutions, Insertion after Remove(IAR), is devised for the simulated annealing. The IAR operation uses the technique of enumerating positions in Sequence Pair and greatly accelerates the searching. Moreover, based on the analysis of diverse objective functions used in the existing researches, we suggest a new objective function, which is still effective when combined with other objectives, for the fixed-outline floorplanning. Compared with the previous fixed-outline floorplanners, the proposed method is effective and efficient. Experiments showed that the proposed fixed-outline floorplanner achieved 100% success rate efficiently when optimizing area and wire-length simultaneously, while getting much smaller wirelength. On the other hand, we validated once more by experiments that aspect ratio close to one is beneficial to wire-length.

This paper studies the buffer planning problem for interconnect-driven floorplanning. With development of deep submicron technology, interconnect plays dominant role and buffer-insertion is a most flexible and efficient way to resolve this problem. However, buffer-planning on a fixed topology which only optimizes area or total wire-length is not reasonable and at the same time, trying to generate a topology which optimizes timing is much too time-consuming. We develop an algorithm which exchanges blocks of similar size to optimize timing constraint. With this algorithm applied, based on a topology which has already optimized area, we generate a packing that doesn't increase total area but exchanges block's position so that interconnect performance could be optimized in reasonable time.

The dominating contribution of interconnect to system performance has made it critical to plan the resources of the buffers and routes in the early stage of the layout. In this paper, we integrate floorplanning with buffer insertion for performance-driven design processes. We devise a two-step method to evaluate the feasible buffer insertion sites, which can improve the efficiency of the buffer-planning algorithm. By partitioning all empty spaces into blocks in the packing process, the buffer allocation is handled as an integral part of the floorplanning. Our buffer-planning algorithm maps the buffers into tiles with consideration of routing congestion. In this approach, we construct a distribution graph to model the possible routes. The buffer allocation method is performed on the updated distribution graph to find the buffer locations with their respective congestion costs. The method is based on a simulated annealing approach, which is composed of multiple phases to speed up the optimization. Since there is more freedom with floorplan optimization, the empirical results demonstrate better performance.

This paper studies the buffer planning problem for interconnect-centric floorplanning for nanometer technologies. The dead-spaces are the spaces within a placement that are not held by any circuit block. In this paper, we proposed a buffer planning algorithm based on dead space redistribution to make good use of dead-spaces for buffer insertion. Associated with circuit blocks under topological representations, the dead space can be redistributed by freely moving some circuit blocks within their rooms in the placement. The total area and the topology of the placement keep unchanged while doing the dead space redistribution. The number of nets satisfying the delay constraint can be increased by redistributing the dead space all over the placement, which has been demonstrated by the experimental results. The increment of the number of nets that satisfy delay constraints is 9% on an average.

Solution space smoothing allows a local search heuristic to escape from a poor, local minimum. In this paper, we propose a technique that can smooth the rugged terrain surface of the solution space of a placement problem. We design the solution space smoothing algorithms for VLSI placement with pre-placed modules and placement with consideration of congestion. Experiment results demonstrated that solution space smoothing is very efficient for VLSI module placement, and it can be applied to all floorplanning representations proposed so far.

By dividing the packing area into routing tiles, we can give the budget of the buffer insertion. And the detail locating of the blocks in their rooms can be implemented for each iterations during the annealing process to favor the later buffer planning. The buffer insertion will affect the possible routes as well the congestion of the packing. The congestion estimation in this paper takes the buffer insertion into account. So we devise a buffer planning algorithm to allocate the buffer into tiles with congestion information considered. The buffer allocation problem is formulated into a net flow problem and the buffer allocation can be handled as an integral part in the floorplanning process. Since there is more freedom for floorplan optimization, the floorplanning algorithm integrated with buffer planning can result in better performance and chip area.

Previous works on buffer planning are mainly based on fixed die placement. It is necessary to reduce the complexity of computing the feasible buffer insertion sites to integrate the buffer planning with the floorplanning process. In this paper, we give an efficient buffer planning algorithm with linear complexity by computing all the feasible buffer insertion sites in a 2-step method. By partitioning all the dead spaces into blocks while doing the packing, the buffer allocation can be handled as an integral part in the floorplanning process. Our method is based on a simulated annealing approach which is divided into two phases: timing optimization phase and buffer insertion phase. Since there is more freedom for floorplan optimization, the floorplanning algorithm integrated with buffer planning can result in better time performance and chip area.