A method is presented for simulation with two zillion and three values. The values that are propagated by the simulation include the familiar 0, 1, and X and also a collection of named unknowns and their formal negations. Each value fits into a single computer word. Applications of this restricted symbolic evaluation include design rule checking for circuits with embedded arrays and timing verification. The authors explore these two applications briefly. By carefully choosing rules for combining the two zillion and three values, and the representations of the values, it is possible to make simulation surprisingly efficient. The authors present two variants and an implementation of each. Both are fast; the faster one sometimes yields less information.>

The High-Speed Simulator (HSS) is a fast and flexible system for gate-level fault simulation. Originally limited to combinational logic, it is being extended to handle sequential logic. It may also prove useful as a functional simulator. The speed of HSS is obtained by converting the cycle-free portions of a circuit into optimized machine code for a general-purpose computer. This compiled code simulates the circuit's response for 16 or 32 test patterns in parallel. Faults are injected into the circuit by changing the machine instruction corresponding to the fault location. From the range of speeds seen in recent measurements, we take 240 million gates per second as a fair general estimate of the speed of 2-valued simulation running on a 3081/K computer. For 3-valued simulation, divide by 2.9. The paper discusses the merits and drawbacks of the HSS strategy. It also sketches the extensions of HSS to model sequential logic and the various applications of HSS. These include functional verification, design for testability, good machine signatures, and accurate simulation of transistor-level defects in certain CMOS technologies. Finally, there is some discussion of how the simulation requirements of future designs can be met, and of the lessons to be drawn from long-term experimentation with HSS.

Several methods for testing VLSI chips can be classified as signature methods. Both conventional and signature testing methods apply a number of test patterns to the inputs of the circuit. The difference is that a conventional method examines each output, while a signature method first accumulates the outputs in some data compression device, then examines the signature - the final contents of the accumulator - to see if it agrees with the signature produced by a good chip. Signature testing methods have several advantages, but they run the risk that masking may occur. Masking is said to occur if a faulty chip and a good chip behave differently on the test patterns, but the signatures are identical. When masking occurs, the signature testing method will incorrectly conclude that the chip is good, whereas a conventional method would discover that the chip is defective.