Convolutional Neural Networks (CNNs) require costly hardware for real-time processing due to massive multiplications. In video-based inference, many pixels remain unchanged between frames. By skipping these operations and reusing previous results, CNNs can be accelerated without accuracy loss. However, efficient implementation of sparse operations is challenging due to the need for change detection and sparse operations in each layer. To address this, we propose Temporal RegionDrop, which performs change detection once per frame and uses a common mask to reduce conversion costs between sparse and dense formats. This method is applicable to all CNNs without retraining. We evaluate our RegionDrop on AGX Orin GPU with ChangeDetectionNet, MOT15, and JHMDB datasets. RegionDrop achieves a 2.0× –6.5× speedup with minimal accuracy loss.

In recent years, there has been a growing need to perform object detection at the edge. Since the edge environment has tight physical constraints, the efficient use of AI devices is a key challenge to executing object detection at high throughput. In this paper, we propose an object detection acceleration method that uses two types of one-stage detectors in combination. After detecting object candidates by a lightweight detector, the method generates aggregated images by combining the candidate images and executes the second, more accurate detector on the aggre-gated images to improve the execution efficiency of AI devices. Our evaluations confirmed that the proposed method could improve object detection throughput by up to eight times for a license plate detection task with almost no accuracy degradation. We also conducted evaluations with a car detection task and a pose estimation task and confirmed the broad applicability of the proposed method.

In recent years, there has been a growing need to perform object detection at the edge. Since the edge environment has tight physical constraints, the efficient use of AI devices is a key challenge to execute object detection at high throughput. In this paper, we propose an object detection acceleration method which uses two types of one-stage detectors in combination. After detecting object candidates by a lightweight detector, the method generates aggregated images by combining the candidate images and executes the second more accurate detector on the aggregated images to improve execution efficiency of AI devices. Our evaluations confirmed that the proposed method can speed up object detection by up to eight times for a license plate detection task with almost no accuracy degradation. We conducted evaluations with a car detection task and a pose estimation task as well and confirmed the broad applicability of the proposed method.

Mobile devices such as smartphones have various restrictions in terms of resources such as batteries and processors. The load reduction on the mobile devices is possible by offloading, migrating application to the resource-rich environment such as cloud servers. However, further study is required on multi-tier environment which contains multiple resources composed of edge servers and cloud servers. This paper proposes an offloading system based on estimated response time (ERT) in multi-tier environment which contains multiple resources. The proposed offloading system calculates ERT based on the state of network and computation resources of each execution resource. Offloading is executed on execution resources with the minimum ERT. We implemented the prototype of the proposed offloading system and evaluated the performance.

Emergency Rescue Information Sharing System gathers information about victims and provides it. In disaster, usable bandwidth is not enough and there are many requests for communication. If information about victims is continuously transmitted to a link whose bandwidth is compressed, congestion of the link occurs, causing delay or loss of information. Therefore, in order to prevent information loss and delay, transmitting information in consideration of the bandwidth of wireless links is important. In this poster, we propose a congestion control method by adjusting transmission speed of information on victims and load balancing to each wireless link.

Quantum Annealing (QA) is an emerging technique, derived from Simulated Annealing, providing metaheuristics for multivariable optimisation problems. Studies have shown that it can be applied to solve NP-hard problems with faster convergence and better quality of result than other traditional heuristics, with potential applications in a variety of fields, from transport logistics to circuit synthesis and optimisation. In this paper, we present a hardware architecture implementing a QA-based solver for the Multidimensional Knapsack Problem, designed to improve the performance of the algorithm by exploiting parallelised computation. We synthesised the architecture using as a target an Altera FPGA board and simulated the execution for solving a set of benchmarks available in the literature. Simulation results show that the proposed implementation is about 100 times faster than a single-thread general-purpose CPU without impact on the accuracy of the solution.

Network Function Visualization (NFV) is becoming a new networking architecture for telecom carriers. NFV achieves network functions with software and commercial off the shelf (COTS) servers instead of dedicated hardware. While the software-based approach is expected to reduce costs, it could cause performance issues. CPU-FPGA tightly coupled architectures may be available in COTS servers in the near future. This paper proposes accelerating NFV application leveraging such a CPU-FPGA architecture. The proposed method of acceleration uses a data plane development kit (DPDK) ring queue, which is often used in network software, as the communication interface between the FPGA and CPU. We propose two optimizations for ring operation and table lookup operation to efficiently use the bus between FPGA and CPU. We evaluated the proposed method with an actual CPU+FPGA based platform, and an NFV application, i.e., vCPE. The results revealed that the evaluation system could accommodate 2 × 40-GbE Internet traffic, and could increase capacity as a vCPE server by x1.33.

IoT(Internet of Things), which collects various data in real world and analyzes values from collected data is one of good methods to help solve such serious problems and to construct efficient social systems. Meanwhile, since collected data is very complicated and has huge size, it takes a long time to collect and analyze “Complicated Big data”. Then, efficient computer systems and efficient network systems are necessary. Integration of heterogeneous computing and 5G network is one of the best platforms to provide complex IoT systems and services. In this paper, first, a reason why complex IoT systems require high performance hetero computing and high-speed communication systems like as 5G is presented. In the next, some use cases of IoT systems infrastructures empowered by hetero computing are also introduced.

This paper proposes a new high-speed method of approximating system reliability. This method is an improved version of truth table approximation. While truth table approximation is simple and widely applicable, its approximation error becomes unreasonably poor as the failure probabilities of the components become worse. Here, we improve its accuracy. The key idea is to use information of non-enumerated states in the approximation process. Numerical examples demonstrate its improved accuracy without increasing the evaluation time.

Context: There is a pervasive feeling that somehow software assurance is important. For example, national space agencies, such as the National Aeronautics and Space Administration (NASA) and the Japan Aerospace Exploration Agency (JAXA), require assurance for their critical software systems. Their assurance effort goes beyond testing, and includes activities such as process compliance checks, artifact audits, and traceability validation. These activities can be costly and their benefits, particularly in managing risk, are poorly understood. This inevitably leads to tough questions concerning value such as "Is assurance worth doing?" and "How much assurance do we actually need?"

The SIMD (single instruction, multiple data) control style achieves a very cost effective processor element (PE) control mechanism. In this paper, two efficient data transfer operations for a SIMD PE array processor are proposed to address the inefficiency of most SIMD processor arrays in performing irregular memory access per PE. First, the SIMD random access provides simultaneous data transfer of randomly, from each PE independently addressed elements. Second, the SIMD ROI (region of interest) access enables concurrent data transfer of ROI areas with optional different ROI parameters for each PE. Speed-up values for both new transfer operations show an at least six times faster execution and the synthesis output reports an area increase of merely 1% for a 32 PE SIMD array processor configuration.

To achieve energy reduction for instruction memory access in VLIW ASIPs, operation shuffling technique has been proposed. The shuffling technique changes assignment of an operation to different slot so that L0 cluster configuration can be improved. The published technique, however, moves operations within a cycle, not between cycles. As a result, the potential gain of energy reduction was limited. This paper proposes a shuffling technique that also moves operations between cycles as well as within a cycle. The experimental results show that the proposed method achieves more efficient energy than the best known shuffling method by up to 15.3% in the best case.

Clustering L0 buffers is effective for energy reduction in the instruction memory hierarchy of embedded VLIW processors. However, the efficiency of the clustering depends on the schedule of the target application. Especially in heterogeneous or data clustered VLIW processors, determining energy efficient scheduling is more constraining. This article proposes a realistic technique supported by a tool flow to explore operation shuffling for improving generation of L0 clusters. The tool flow explores assignment of operations for each cycle and generates various schedules. This approach makes it possible to reduce energy consumption for various processor architectures. However, the computational complexity is large because of the huge exploration space. Therefore, some heuristics are also developed, which reduce the size of the exploration space while the solution quality remains reasonable. Furthermore, we also propose a technique to support VLIW processors with multiple data clusters, which is essential to apply the methodology to real world processors. The experimental results indicate potential gains of up to 27.6% in energy in L0 buffers, through operation shuffling for heterogeneous processor architectures as well as a homogeneous architecture. Furthermore, the proposed heuristics drastically reduce the exploration search space by about 90%, while the results are comparable to full search, with average differences of less than 1%. The experimental results indicate that energy efficiency can be improved in most of the media benchmarks by the proposed methodology, where the average gain is around 10% in comparison with generating clusters without operation shuffling.