Previous schemes for designing secure branch prediction unit (SBPU) based on physical isolation can only offer limited security and significantly affect BPU’s prediction capability, leading to prominent performance degradation. Moreover, encryption-based SBPU schemes based on periodic key rerandomization have the risk of being compromised by advanced attack algorithms, and the performance overhead is also considerable. To this end, this paper proposes conflict-invisible SBPU (CIBPU). CIBPU employs redundant storage design, load-aware indexing, and replacement design, as well as an encryption mechanism without requiring periodic key updates, to prevent attackers’ perception of branch conflicts. We provide a thorough security analysis, which shows that CIBPU achieves strong security throughout the BPU’s lifecycle. We implement CIBPU in a RISC-V core model in gem5. The experimental results show that CIBPU causes an average performance overhead of only 2.9%–4.0% with acceptable hardware storage overhead, which is the lowest among the state-of-the-art SBPU schemes. CIBPU has also been implemented in the open-source RISC-V core, SonicBOOM, which is then burned onto an FPGA board. The evaluation based on the board shows an average performance degradation of 2.01%, which is approximately consistent with the result obtained in gem5.

Transient execution attacks can exploit speculative execution to leak sensitive information through cache systems. Consequently, numerous cache-centric secure speculation defenses have been proposed. However, as we demonstrate both theoretically and empirically, these defenses remain vulnerable to data leakage because they neglect or fail to fully address the security issues posed by the hardware prefetcher, a critical component of modern cache systems, within the speculative execution path. In this work, we develop a new attack framework, SpectrePrefetch, which exploits hardware prefetchers as transmission mediums for leaking secrets during speculative execution. Specifically, we introduce two variants of SpectrePrefetch attacks that encode transient secrets into the prefetching patterns and prefetching confidence, respectively, and then recover secrets by probing the cache state or the prefetcher state. We launch SpectrePrefetch to attack several Intel CPUs and a Gem5 simulator, demonstrating its feasibility, robustness, bandwidth, scalability, and security implications on existing defenses. The results show that SpectrePrefetch can leak secrets at a high rate of 31.25 Kbps with an accuracy of 98.87%. More seriously, SpectrePrefetch undermines cache-centric secure speculation defenses or even secure cache designs, and is challenging to mitigate. Our experimental results show that simply restricting the prefetcher to update only on committed instructions, as proposed in MuonTrap, nearly loses all performance benefits provided by hardware prefetching. Finally, we propose a low-cost, scalable non-deterministic prefetching defense against transient execution attacks exploiting hardware prefetchers, while maintaining or even improving average performance on SPEC2017 benchmarks.

In recent years, with an increasing number of Internet of Things (IoT) devices, general cloud computing mode is hard to process large amounts of data with high Quality of Service (QoS). Edge computing is put forward to relieve the pressure of cloud servers, but most of them only focused on allocating tasks depending on cloud servers or edge servers with the virtualization technology. Resource-constrained smart mobile terminals (RC-SMTs) produce most of the data to be processed but some of them are usually not able to support even Docker technology. The cooperative computation capacity of RC-SMTs is potential but is often neglected by most researchers. However, there is little research focus on edge computing only among RC-SMTs without computing ability supported by servers. For this reason, this article proposes a framework named data-drive task offloading with a unified resource model (DDTO-URM) to manage the limited resource of IoT which enables the allocation of tasks constantly generated from the edge of the network. Then, a meta-heuristic algorithm called grouped crossover genetic algorithm (GCGA) is designed to obtain task offloading strategy under a resource-constrained environment. As a result, the computation capacity of the system is enhanced to cover the requirement by improving the utilization of RC-SMTs. Through the analysis of simulation, the proposed approach can deal with the problem of DDTO-URM better than benchmark algorithms under constraints, ensuring the real time and ultralightweight of the collaborative edge-computing system.

The expansion of Internet of Things (IoT) spawns large on-device machine learning demands, while the machine learning can be a hard task for resource constrained IoT terminals with fragmented data set. Federal learning (FL), which aims to build a joint model across multiple devices, IoT-FL has now become a promising path for learning on terminals. In broad FL fields, current server–client pattern cannot jump out of the third-party self-trustless problem, and recent researches suggest that even sharing training results may also reveal the raw data sets. Homomorphic encryption (HE) is a powerful method in privacy preserving, while so far it is hard to apply HE into multiparty computing (MPC) scenarios including FL. Combining with the existing IoT architecture, in this article, we customize a scheme (FL chain) dedicated for the privacy and trustiness issues in IoT-FL scenarios, which integrates blockchain smart contract and HE. Differ from traditional schemes, our FL chain is highly adaptive with current IoT architecture and it is the first scheme that applied HE into IoT-FL privacy preserving. Theoretical analysis and experimental results prove the feasibility of FL chain.

Modern processors make use of optimization techniques such as cache and speculation mechanisms to greatly improve performance. But recent research has found that these techniques can also be exploited by attackers to perform powerful side-channel attacks. A large number of powerful cache-based attacks have been replicated and enhanced over Intel X86- and ARM-based architectures, but there is a relative lack of research on RISC-V-based architectures. Xuantie-910 and BOOM are both RISC-V-based processors. So far, cache-side channels in the unprivileged case of Xuantie-910 have not been proven, while cache attacks against BOOM are proliferating. There are two types of caches, including physically-indexed physically-tagged (PIPT) cache (adopted by Xuantie-910) and virtually-indexed physically-tagged (VIPT) cache (adopted by BOOM), corresponding to two different cache addressing forms. VIPT has higher addressing performance than PIPT, since it can directly obtain cache line index from virtual address. In this paper, we study Xuantie-910 and BOOM to explore the impact of cache design on the security of RISC-V-based microarchitecture. Specifically, we compare the impact of their cache addressing forms on precise flushing of cache lines at specified locations, which plays an important role in cache side-channel attacks. Experimental results show that for the VIPT cache in BOOM, the location-specified cache lines can be accurately flushed, and Spectre attack can be successfully carried out by using the cache side-channel. On the other hand, for the PIPT cache in Xuantie-910, it is impossible for attackers to directly and accurately flush the specified location of cache without affecting performance, which hinders the success of cache side-channel attacks. This provides us with an insight that one can adopt a VIPT-based cache with a mechanism similar to PIPT for preventing the accurate access of cache line index, which can not only keep the advantage of high-performance addressing in VIPT but also improve chip security.

This paper presents a study on some approaches in face reconstruction and the methodology used. The results and drawbacks of each method are discussed. To construct the 3D face model there are some methods which select the features automatically or manually. First a method in textured 3D face reconstruction using two 2D images from any angle is discussed which does not need any particular database, but it has to define the feature points manually. Then we describe automatic 2D to 3D face reconstruction from a single frontal face image which needs the use of USF Human ID 3-D database. Afterwards we talk about a Model Based Face Reconstruction for Animation. We also describe briefly about 3D face modeling by fusing multiple 2D images which is fully automatic and via an EM approach which uses the shape and pose parameters. Finally we describe a Rapid Modeling of Animated Faces from Video method and 2D face reconstruction using a minimum set of feature points.

In this paper, we propose a new approach for face pose estimation based on two images from different views under certain conditions. Using a weak-perspective imaging model, six pose parameters were deduced, with four pairs of feature points properly chosen across the two face images. Through the scan-iteration algorithm, a robust performance was achieved, without solving non-linear equations. Comparing to some other methods which estimate rotation matrix based on fundamental matrix (F), our method focuses on the "absolute pose" with respect to front view rather than the "relative pose" between the two face images. "Absolute pose" is indispensable in most situations especially for 3D face modeling. Since our method does not depend on any 3D face models and frontal-view images, it can be applied not only to face recognition and 3D face modeling, but also to other relevant applications. Experimental results demonstrate the efficiency of our method