This paper presents a 915 MHz ultra-low-power (ULP) receiver based on a single-path third-harmonic mixing (SPTHM) architecture. Unlike conventional multi-path sub-harmonic receivers that require precise multi-phase local oscillators (LOs), this work simplifies the receiver to a single-mixer path architecture by jointly optimizing the LO harmonic order and duty cycle. The receiver is driven by a 10%-duty-cycle LO operating at one-third of the carrier frequency ($f_{\mathrm {c}}$). Compared to the typical 50%-duty-cycle LO in the SPTHM configuration, the proposed receiver improves the conversion gain by 12.1 dB and noise figure (NF) by 5.2 dB. The architecture also exhibits a front-end NF variation of less than 1 dB across the 3%-13% LO duty-cycle range, thereby relaxing constraints on pulse generation. To facilitate ULP channel selection, a comparison-skipped frequency-locked loop (FLL) is used, consuming just$5~\mu $W. A high-Q IF amplifier with an improved active inductor load is incorporated to enhance in-band interference rejection, achieving 31 dB signal-to-interference ratio (SIR) at 5 MHz offset. Fabricated in a 65 nm CMOS, the receiver achieves a sensitivity of −86 dBm at 250 kbps data rate with a$39.4~\mu $W power consumption, including an on-chip LO. It indicates a competitive figure-of-merit (FoM) of 184 dB within a compact active area of 0.16 mm2.

The closed-loop deep brain stimulation system demands high-performance seizure detection, especially in terms of ultra-low power consumption and patient specificity. In this paper, we propose a seizure detection approach featuring low-pass filters for feature extraction and a programmable linear support vector machine for classification. This approach effectively reduces power consumption while retaining the signal energy near the cutoff frequencies and preserving the correlation between adjacent frequency bands. To reduce the false alarm rate, a Hidden Markov Model is utilized for post-processing. The proposed processor also employed calculation bit-width optimization and time-division multiplexing to minimize power and area consumption, while maintaining minimal accuracy loss. Implemented in a 65-nm CMOS process, the processor occupies an active area of 0.14 mm2. It achieves an energy classification efficiency of 0.473 μJ/class with 0.7-V supply and 16.384-kHz system clock. The measurement results show a sensitivity of 95.92%, a specificity of 98.11%, and a false alarm rate of 1.78 times/h, as validated by the CHB-MIT dataset.

This paper presents a reference double-sampling phase-locked loop (RDSPLL) that integrates frequency multiplication and octa-phase clock generation into a single system, significantly reducing power consumption. A differential ring oscillator (DRO) is employed to generate octa-phase clocks with high phase accuracy. The reference double-sampling technique extends the loop bandwidth, effectively suppressing phase noise from the ring oscillator and thereby reducing jitter. To achieve accurate and efficient phase error detection, we proposed a novel offset-compensated hybrid phase detector (OCH-PD), featuring an offset calibration and a comparator-ADC hybrid quantizer. The offset calibration utilizes the CDAC to dynamically compensate for the mismatch in double-sampling, improving jitter and spur performance. The hybrid quantizer supports dynamic mode switching based on different locking states: during the coarse frequency locking phase, it operates in the ADC mode to accelerate the locking process; once a stable lock is achieved, it switches to the comparator mode to enable low-power, high-speed quantization. Fabricated in a 65-nm CMOS process, the prototype achieves 674 fs RMS jitter at 2.4 GHz while consuming only 3.43 mW, resulting in a$\text {FOM}_{\text {Jitter-N}}$of -251.9 dB. With offset calibration, the reference spur at 100 MHz is suppressed from -56 dBc to -80 dBc, and the jitter is reduced from 1.42 ps to 674 fs. The locking time improves from$10.5~{\mu }$s to$1.6~{\mu }$s using the hybrid quantizer. The eight-phase accuracy remains better than 1° over the frequency range of 2-2.8 GHz.

Radar is an extremely valuable sensing technology for detecting moving targets and measuring their range, velocity, and angular positions. When people are monitored at home, radar is more likely to be accepted by end-users, as they already use WiFi, is perceived as privacy-preserving compared to cameras, and does not require user compliance as wearable sensors do. Furthermore, it is not affected by lighting conditions nor requires artificial lights that could cause discomfort in the home environment. So, radar-based human activities classification in the context of assisted living can empower an aging society to live at home independently longer. However, challenges remain as to the formulation of the most effective algorithms for radar-based human activities classification and their validation. To promote the exploration and cross-evaluation of different algorithms, our dataset released in 2019 was used to benchmark various classification approaches. The challenge was open from February 2020 to December 2020. A total of 23 organizations worldwide, forming 12 teams from academia and industry, participated in the inaugural Radar Challenge, and submitted 188 valid entries to the challenge. This paper presents an overview and evaluation of the approaches used for all primary contributions in this inaugural challenge. The proposed algorithms are summarized, and the main parameters affecting their performances are analyzed.

A prototype of fully flexible intelligent contact lens, which are shown in the impressive action movie series of “MISSION: IMPOSSIBLE”, has become the Possible Mission in this work. Hereon, the system adopts analog-to-information processing method to build a specific Multi-Layer Perceptron network for image classification tasks with flexible devices and circuits, where the information is extracted from raw data of the sensing analog signal directly. Simulated with HSPICE of Level-62 TFT device model, for standard test image data set of MNIST, the classification accuracy of the presented flexible neural network circuit is up to 92.99%; meanwhile, the classification speed is as fast as 10k fps, and the energy consumption is low to only 15.16μJ. Additionally, for the imperfections of flexible devices of larger devices mismatch and process variations, the fault-tolerance of the system has been evaluated as well, which demonstrates the feasibility of the presented methods and lowers the barrier to integrated all kinds of FLEXIBLE Devices into a FULLY FLEXIBLE Systems with sensors, processing parts and even energy harvesting parts, etc., in the future wearable smart terminals.