Power distribution network (PDN) optimization in 2.5-D chiplet architectures represents a critical bottleneck as designs scale to 100+ integrated chiplets, where decoupling capacitor placement becomes a multi-port optimization challenge requiring millions of expensive electromagnetic (EM) simulations. Current state-of-the-art (SOTA) methods - from genetic algorithms (GA) to reinforcement learning (RL) - treat PDN as black-box functions, failing to exploit inherent physical structure and scaling exponentially with problem complexity. We introduce Φ-BO, the first physics-informed Bayesian optimization (BO) framework specifically designed for multi-port decoupling capacitor placement in 2.5-D chiplet PDN. Our key innovation systematically integrates EM field theory into machine learning (ML) optimization through novel spatial feature transformations and Multi-Port Aware Transformation (MPAT), enabling a paradigm shift from black-box to physics-aware optimization. This approach captures spatial dependencies and port coupling effects, dramatically reducing effective problem dimensionality while enabling intelligent exploration of discrete placement configurations. Demonstrated on a 22-chiplet RISC-V processor design, Φ-BO achieves 23% impedance improvement, and 3 × faster convergence compared to SOTA methods.

Power supply noise has emerged as a critical bottleneck in modern integrated circuit design, where increasing current densities and higher operating frequencies pose significant challenges to system reliability. While decoupling capacitors (decaps) serve as the primary solution for suppressing power delivery network (PDN) noise, determining their optimal values and placement remains computationally prohibitive using traditional methods. This aritcle introduces ConvGA, a novel framework that seamlessly integrates convolutional neural networks (CNN) with genetic algorithms to revolutionize PDN decap optimization. At the heart of ConvGA is a specialized CNN architecture trained on comprehensive boundary element method (BEM) simulations, enabling ultra-fast impedance prediction for arbitrary PCB configurations. Our CNN achieves remarkable accuracy while reducing impedance computation time from hours to mere milliseconds—a 500× speedup over conventional BEM calculations. This acceleration enables the genetic algorithm to efficiently explore vast design spaces through adaptive population control and dynamic constraint mechanisms, systematically minimizing both the number of required capacitors and the deviation from target impedance. Extensive experiments on industrial-scale PDNs demonstrate that ConvGA achieves a 15× reduction in optimization time while requiring 30% fewer capacitors compared to state-of-the-art methods, consistently producing high-quality solutions across diverse PDN configurations.

With the advancement of modern nanoscale technology nodes, Static Timing Analysis (STA) has become an indispensable technique for ensuring circuit reliability and performance across diverse process conditions. However, traditional STA methods scale poorly to the explosion of process corners in the nanoscale fabrication technology. Despite some seminal works in using AI to accelerate such processes, they either lack reliability or stability. To this end, we introduce ASAP, a novel approach addressing this challenge by combining both the latest deep learning methods and the classical Bayesian models to deliver scalable and accurate predictions with a self-calibration strategy to ensure reliability. Technically, the ASAP novelly integrates self-attention to help identify and prioritize crucial features under various input conditions and employs Neural Process to make confidence-based predictions for the final timing results. Furthermore, ASAP is equipped with Active Learning for self-refinement and self-correction. Experimental evaluations on benchmark circuits demonstrate that our method surpasses state-of-the-art work in STA accuracy by 18% in terms of prediction accuracy.

The placement of analog Integrated Circuits (ICs) plays a critical role in their physical design. The objective is to minimize the Half-Perimeter Wire Length (HPWL) while satisfying complex analog IC constraints, such as symmetry. Unlike digital ICs, analog ICs are highly sensitive to parasitic effects, making device symmetry crucial for optimal circuit performance. However, existing methods, including both machine learning-based and analytical approaches, struggle to meet strict symmetry constraints. In machine learning-based methods, training a general model is challenging due to the limited diversity of the training data. In analytical methods, the difficulty lies in formulating symmetry constraints as a convex function, which is necessary for gradient-based optimization of the placement. To address the issue, we formulate the placement process as a Markov decision process and propose SACPlace, a multi-agent deep reinforcement learning method for Symmetry-Aware analog Circuit Placement. SACPlace initially extracts layout information and various constraints as the input information for placement refinement and evaluation. Subsequently, SACPlace constructs multi-agent policy networks for symmetry-aware placement by refining placement guided by the evaluation of optimal symmetry quality. Following this, SACPlace constructs multilayer perceptron-based critic networks to embed placement information for evaluating symmetry quality. This evaluation reward will be used for guiding placement refinement. Experimental results from four public analog ICs instances demonstrate that our method achieves the lowest actual wirelength and area while fully satisfying symmetry and common constraints, outperforming state-of-the-art methods. Additionally, simulation results on real-world analog ICs show better performance than these methods and even manual designs.

With the slowdown of technology node scaling, 2.5D Chiplet technology has emerged as a promising approach to sustain Moore’s Law. When routing clock signal on the passive interposer layer, transmission line effect must be considered, as signal rise/fall delay becomes comparable to propagation delay, significantly impacting signal integrity and system performance. Additionally, since active devices cannot be placed on the passive interposer, buffers can only be inserted in the chiplets mounted on the interposer. This paper investigates the problem of clock network synthesis for a 2.5D Chiplet with a passive interposer. Firstly, we propose to use a transmission line model to evaluate inter-chip clock skew and delay accurately. Then, we propose a clock network synthesis method considering transmission line effect and impedance matching. Finally, we propose a buffer insertion method with minimum clock wire detouring on passive interposer in order to optimize the inter-chiplet clock network. Experimental results show that our fast transmission line model can calculate clock skew more accurately compared to conventional Elmore model and only results in 2.4% error compared to HSPICE simulations. The clock network syntheses on several 2.5D Chiplet benchmarks show that our proposed algorithm is effective to construct zero-skew clock network for a 2.5D Chiplet in terms of clock skew and buffer area.

As Cu interconnects near their physical limits with continued technology scaling, carbon nanotube (CNT) interconnects have emerged as a promising alternative due to their excellent conductivity. However, fabrication immaturity introduces significant process variations, causing discrepancies between ideal and actual performance. This article presents a novel approach to optimize CNT interconnects considering process variations. We first develop a parameterized CNT interconnect model that accounts for process variations. Using this model, a Bayesian Neural Network (BNN) is proposed to predict performance distributions by leveraging its inherent uncertainty. We then introduce a Bayesian optimization framework that uses the BNN’s posterior to jointly optimize interconnect parameters and buffer insertion, targeting Area-Delay Product (ADPIn this work, we use area-delay product ziegler2001optimal as the performance metric, though other metrics can also be applied within our framework.) with process variations. Experimental results demonstrate the effectiveness of our approach. The proposed BNN model achieves over 95% prediction accuracy for interconnects performance distributions. Compared to existing methods, our method achieves an average ADP improvement of 20.3% over the state-of-the-art methods and 13% over the standard Monte Carlo method. Compared with Monte Carlo method, our method also achieves an average 8.8x acceleration. Moreover, the optimized CNT interconnects show an average improvement of 82.8% in ADP and 68.7% in delay compared to Cu interconnects. This work offers an effective method for optimizing CNT interconnects under process variations and highlights their potential as a viable alternative to Cu interconnects in future integrated circuits.

Object detection in aerial remote sensing images is essential for applications such as traffic management, public security, and ecological monitoring. However, existing methods struggle to handle multi-scale objects, complex backgrounds, and frequent occlusions, resulting in inadequate global feature extraction and unstable multi-scale loss calculations. To address these challenges, we propose the Multi-Feature Attention-Enhanced YOLO (MFAE-YOLO) network. Our approach introduces a Global Feature Fusion Processing (GFFP) module to enhance global feature extraction. The backbone network incorporates Fusion of Channel, Pixel, and Spatial (FCPS) attention modules to strengthen feature representation, while C2F-Feature Pool Extraction Units (C2F-FPEU) optimize pooling-based feature extraction. Additionally, we propose an Accurate IoU (AIoU) loss function to refine bounding box regression. Experiments on NWPU VHR-10, RSOD, and DIOR datasets demonstrate that MFAE-YOLO surpasses state-of-the-art methods, achieving mAP50values of 94.7%, 94.8%, and 67.0%, respectively. Ablation studies further validate the contributions of each module. The code is available at https://github.com/yiboCode/MFAE-YOLO.

As the prevailing copper interconnect technology advances to its fundamental physical limit, interconnect delay due to ever-increasing wire resistivity shows a significant impact on circuit performance. Bundled single-wall carbon nanotubes (SWCNTs) interconnects have emerged as a promising candidate technique to replace copper interconnects thanks to their superior conductivity and immunity to electromigration. To deliver satisfying performance within low power consumption, the CNT interconnect timing is optimized by adjusting either the interconnect geometry, e.g., CNT diameter and nanotube pitch, or the buffer insertion. These two operations are normally optimized separately, which leads to an inferior design that is not global optimum. To resolve this problem, we first propose a model that parameterizes SWCNT interconnects. We then leverage the known Bayesian optimization to optimize SWCNT global interconnect and buffer insertion simultaneously to promote interconnect performance. The proposed method is assessed based on a set of interconnect benchmarks at 22nm technology node. Compared to the state-of-the-art methods, the Bayesian co-optimization technique can reduce more than 17% power delay product (PDP). Additionally, we evaluate the SWCNT interconnect performance at 32nm, 22nm and 16nm technology nodes. Compared to the SOTA method with the same wire dimension, SWCNT interconnects optimized by the proposed method can further reduce delay and PDP relative to copper by 35% and 45% on average, which highlights the promising prospect of the SWCNT interconnect technology and the effectiveness of our proposed technique.

One of the most significant technical research challenges of space-air-ground-sea integrated networks is to realize satisfactory wireless data transmission in underwater environments. However, although numerous types of communications, e.g., radio frequency, optical and acoustic, have been investigated, the performance of wireless underwater communications still cannot satisfy the ever-increasing high data rate and long communication distance requirements. This paper demonstrates an early attempt regarding performance analysis of acoustic intelligent reflecting surface (RIS)-assisted wireless underwater communication. The minimization of transmission power is formulated subject to a list of constraints. The analytic scheme is proposed, where two key system parameters, e.g., reflection angle and acoustic signal frequency, are investigated. Numerical results verify that acoustic RIS-assisted wireless underwater communication can significantly enhance signal transmission quality and decrease interference. The results obtained in this paper can be applied to future autonomous underwater vehicles and robot system designs.

Unmanned surface vehicles (USVs) are becoming increasingly significant in fulfilling integrated sensing, computing, and communication with the emergence of bidirectional computation tasks. However, Quality-of-Service provisioning is still challenging since USVs are restricted with limited onboard resources and direct links between them and shore-based terrestrial base stations (TBSs) are frequently blocked. This article proposes a novel reconfigurable intelligent surface (RIS)-assisted cooperative unmanned aerial vehicle (UAV)–USV mobile-edge computing (MEC) network architecture, where RIS-mounted tethered UAV (TUAV) and rotary-wing UAVs (RUAVs) are collaboratively utilized to serve USVs. RUAVs energy minimization is formulated by jointly considering TUAV hovering altitude, RIS phase-shift vector, RUAV service selection indicator, and RUAVs turning points. A heuristic solution is proposed to tackle the formulated problem, where the original problem is first decoupled into three subproblems, e.g., the joint optimization of RIS phase-shift vector and TUAV hovering altitude subproblem, RUAVs service selection indicator subproblem, and RUAVs turning points subproblem, each of which is solved by the proposed modified alternative direction method of multiplier (ADMM) algorithm, the proposed enhanced simulated annealing (ESA) algorithm and the proposed successive convex approximation (SCA)-based algorithm. In this way, the challenging problem can be efficiently solved iteratively. The results show that the proposed solution can decrease RUAVs energy consumption by nearly 29% compared to numerous selected advanced algorithms. Moreover, the performance of the proposed solution regarding typical penalty coefficients and number of RIS reflecting elements is investigated.

Unmanned Surface Vehicles (USVs) in inland waterways have drawn increasing attention for their excellent capability to serve maritime time-consuming missions such as autonomous navigation and intelligent monitoring. However, USVs struggle to accomplish emerging computation-intensive tasks (e.g., sensor, telemetry, etc) timely due to the limited on-board resources. This paper proposes a novel reconfigurable intelligent surface (RIS)-assisted unmanned aerial vehicle (UAV) multi-access edge computing (MEC) network architecture to support low-latency USVs data computation with time window. Aiming to enhance USVs task processing efficiency, the minimization of USVs task processing time is formulated by jointly considering UAVs flight route selection, USVs execution mode selection, UAVs hovering coordinates and RIS phase shift vector. A heuristic solution is proposed to tackle the formulated challenging problem iteratively. The original problem is decoupled into three subproblems: an enhanced deferred acceptance algorithm is proposed to solve UAVs flight route selection subproblem; an enhanced Lagrangian relaxation method is proposed to solve USVs execution mode selection subproblem; a joint alternating direction method of multipliers (ADMM)-successive convex approximation (SCA)-based algorithm is proposed to solve UAVs hovering coordinates subproblem. Experiment results demonstrate that the proposed solution can decrease task processing time by approximately 54% compared with numerous selected advanced algorithms. Moreover, the performance of the proposed solution under typical UAVs caching capability and the number of UAVs has been investigated.

We propose a multi-corner multi-stage timing analysis prediction framework using a generalized linear model with latent features. We then further improve such methods using kernel trick extension, transfer learning with knowledge from previous designs, and multi-output feature engineering to deliver state-of-the-art (SOTA) prediction accuracy with very limited training data. Most importantly, our method is equipped with a Bayesian decision strategy to deliver reliable predictions with accuracy close to 100%, pushing the frontier of the machine-learning-based STA for practical implementation in the industry environment, where reliability is highly desired. Experimental results show that the accuracy of our proposed method outperforms the SOTA competitors by up to 4x and can improve prediction accuracy to 100% with little extra STA executions.

In modern electronic manufacturing processes, multi-layer Printed Circuit Board (PCB) routing requires connecting more than hundreds of nets with perplexing topology under complex routing constraints and highly limited resources, so that takes intense effort and time of human engineers. PCB fanout as a pre-design of PCB routing has been proved to be an ideal technique to reduce the complexity of PCB routing by pre-allocating resources and pre-routing. However, current PCB fanout design heavily relies on the experience of human engineers, and there is no existing solution for PCB fanout automation in industry, which limits the quality of PCB routing automation. To address the problem, we propose a neuralized PCB fanout method by deep reinforcement learning. To the best of our knowledge, we are the first in the literature to propose the automation method for PCB fanout. We combine with Convolution Neural Network (CNN) and attention-based network to train our fanout policy model and value model. The models learn representations of PCB layout and netlist to make decisions and evaluations in place of human engineers. We employ Proximal Policy Optimization (PPO) to update the parameters of the models. In addition, we apply our PCB fanout method to a PCB router to improve the quality of PCB routing. Extensive experimental results on real-world industrial PCB benchmarks demonstrate that our approach achieves 100% routability in all industrial cases and improves wire length by an average of 6.8%, which makes a significant improvement compared with the state-of-the-art methods.

In modern advanced integrated circuit design, a design normally needs to be progressively optimized until the static timing analysis (STA) of full process corners meets the timing constraints. To improve efficiency, using machine learning to predict the path timings directly in order to reduce the extensive time-consuming SPICE simulations has become a promising technique to approach fast design closure. However, current methods lack both flexibility and reliability to be used in a practical industrial environment. To resolve these challenges, we propose TOTAL, which is constructed using a generalized linear model with latent features to effectively capture knowledge transferred from previous designs and delivers state-of-the-art (SOTA) prediction accuracy that is up to 6.6x improvement over the competitors in terms of mean absolute error (MAE). Most importantly, TOTAL is equipped with a Bayesian decision strategy to actively update uncertain predictions and deliver reliable predictions with accuracy close to 100%, pushing the frontier of the machine-learning-based STA for practical implementation.

Dynamic Partially Reconfiguration (DPR) on FPGA has attracted significant research interest in recent years since it provides benefits such as reduced area and flexible functionality. However, due to the lack of supporting synthesis tools in the current DPR design flow, leveraging benefits from DPR requires specific design expertise with laborious manual design effort. Considering the complicated concurrency relations among various functions, it is challenging to select appropriate Partial Reconfiguration Modules (PR Modules) and cluster them into proper groups with a proper reconfiguration schedule so that the hardware modules can be swapped in and out correctly during the run time. Furthermore, the design of PR Modules also impacts reconfiguration latency and resource utilization greatly. In this paper, we propose a Maximum-Weight Independent Set model to formulate the PR Module selection and clustering problem so that the original manual exploration can be solved efficiently and automatically. We also propose a step-wise adjustment configuration prefetching strategy incorporated in our model to generate optimized reconfiguration schedules. Our proposed approach not only supports various design constraints but also can consider multiple objectives such as area and reconfiguration delay. Experimental results show that our approach can optimize resource utilization and reduce reconfiguration delay with good scalability. Especially, the implementation of the real design case shows that our approach can be embedded in Xilinx's DPR design flow successfully.

Precharacterizing the transition cubes containing stratified dielectrics is inevitable for the floating random walk (FRW)-based capacitance extraction. Each multilayer-dielectric transition cube is characterized by a pair of Green’s function table (GFT) and weight value table (WVT), and all these GFTs and WVTs usually have large volume and constitute the major memory cost of the FRW algorithm. In this work, we explore the geometric symmetry of the multilayer-dielectric transition cube to enable volume reduction and fast generation of the GFT and WVT. For a general transition cube with stratified dielectrics and the one with four equal-thickness dielectrics, two schemes are proposed to reduce the volume of GFT and WVT by$8\times $and over$10\times $, respectively. Accordingly, an approach for fast generation of the reduced GFT/WVT is proposed, which is proved to produce the same result as the original GFT/WVT values. And, an improved FRW algorithm is proposed to utilize the reduced GFTs/WVTs without the sacrifice of runtime or accuracy. Both theoretical analysis and numerical experiments are conducted to demonstrate the remarkable volume reduction of precharacterization data (GFTs/WVTs). The fast GFT/WVT generation approach and the improved FRW algorithm are also validated with numerical experiments, showing over$10\times $speedup of the precharacterization process, and accurate and memory-efficient capacitance extraction as well.

Since most System-on-Chips (SoCs) consist of heterogeneous IP core(s), application-specific Network on Chip (NoC) architectures are appropriate to meet the design requirements. The energy and performance optimization in the NoC design will continue to be the main design goal in nanoscale technologies. In this paper, we present a new hierarchal partitioning approach considering not only the reduction of wire length among cores, but also the optimization of switching power consumption subject to performance constraints. The experimental results on different benchmarks showed that our NoC topology synthesis algorithm can effectively save power and improve performance.

Multi-core technology becomes a new engine that drives performance growth for both microprocessors and embedded computing. This trend asks chip floorplanners to consider regularity constraint since identical processing/memory cores are preferred to form an array in layout. As chip core count keeps growing, manual floorplanning will be inefficient on the solution space exploration while conventional floorplanning algorithms do not address the regularity constraint. In this work, we investigate how to enforce regularity constraint in a simulated-annealing based floorplanner. We propose a simple and effective technique for encoding the regularity constraint in sequence-pairs. To the best of our knowledge, this is the first work on regularity-constrained floorplanning in the context of multi-core processor designs. Experimental comparison with a semi-automatic method shows that our approach yields an average of 22% less wirelength and mostly smaller area.

As technology advances, the voltage (IR) drop in the Power/Ground (P/G) network becomes a serious problem in modern IC design. The P/G network co-design with floorplan can improve the power design quality. Different with traditional approaches which analyze P/G network during the floorplanning iterations, in this paper, an efficient pattern selection method is used to provide gradient information for fast signal-integrity estimation. We also propose a novel P/G aware incremental algorithm which can intelligently fix the violations during the floorplanning process. The P/G pin assignment and wire sizing method are adopted during the floorplanning process so that the power routing resource can be minimized with the constraints of IR drop and electron migration (EM) considered. Experimental results based on the MCNC benchmarks show that our design not only significantly speeds up the optimization process, but also optimizes the power routing resource while the quality of the floorplanning is maintained.