Neural-recording devices have evolved to capture extensive data from neuronal populations, revealing valuable insights in the neuronal computation through the recordings of action potentials. Extracting this meaningful information from voluminous recordings is essential for unraveling the dynamics of biological neural networks, particularly if performed in real-time, it opens potential applications such as electroceutics and Brain-Machine-Interfaces (BMIs) as a treatment for neurodegenerative diseases. However, neuroprosthetics and BMIs require serious technological constraints regarding accuracy and power consumption. Despite the global interest in spike sorting, most approaches remain limited to offline processing, involve preprocessing steps or some supervision, limiting their potential for automated real-time processing. In this paper, we present the FPGA implementation of an unsupervised Spiking Neural Network (SNN) that performs spike sorting which can be efficiently implemented compared to traditional methods. Through several network optimizations, we are able to implement multiple SNNs for multi-channel processing on a single entry level FPGA with low latency, while maintaining the same accuracy as the software simulation. Moreover, the SNN is seamlessly integrated into a global system benefiting from of the AMD Zynq MPSoC architecture, facilitating efficient data transfer from recording devices to the SNN, and SNN output to custom devices, paving the way toward closed-loop systems which could result in neuroprosthetics and BMIs.

Millions of people are affected by neurological disorders. Brain-Machine Interfaces (BMIs) and neuroprosthesis have been the object of extensive research and may represent a valid treatment for diverse neurological diseases. The realization of neuroprostheses requires technologies to interact with neuronal cell assemblies in the nervous system, and to drive them into a desired state or to produce a specific behavior. One of the best solutions to design this kind of neuroprostheses is to implement a real-time hardware Spiking Neural Network (SNN). Not only will it mimic the electrical behavior of one biological neuron but also the dynamic of a neural network with plasticity rules. In this work, we present digital hardware implementation of biomimetic SNNs for stimulating in vitro cells. By connecting living neurons with electronic SNNs, we are intending to develop a model system for a brain-electronics interface.

Reuse methodologies are now widely used to design digital circuits. They are based on the concept of intellectual property (IP), or virtual block of computing, characterized by a behavioral model, synthesizable or not. The design reuse for analog integrated systems is much less natural and less standardized. This paper addresses the issue of an analog design flow based on reuse, focusing on three key issues: the formal content of the IP block, the design of a reusable analog IP, and the organization of a design flow centered on an IP library. After a conceptual overview, this paper presents the methodological principles and details examples with a tutorial intention. The objective is to guide the designer involved in the process of developing analog IPs and corresponding design flow. This method is inspired by platform-based design and adapted here on an original case study: the design of full-custom neuromimetic integrated circuits, built from specific analog computational blocks. The development of reusable IPs represents an additional effort, mainly for behavioral modeling and characterization. Nevertheless, the steps illustrated in this case study show that the extra time provides a definite advantage to future design projects.

In this paper, we present an hardware implementation of spiking neural networks based on analog integrated circuits. These ICs compute in real-time a biologically realistic neuron models. Each integrated circuit includes five neurons and analog memory cells to set and store the conductance model parameters, and eventually optimize it to compensate the analog circuit variability. The circuits are embedded in a multi-board system all connected to a backplane with daisy-chain facilities. Each action potential computed by analog neuromimetic chips is time-stamped when detected by digital device (FPGA). These FPGAs are also in charge of the real-time plasticity computation and of controlling inter-boards communication. The implemented neural plasticity is also biological relevant thanks to its time dependent computation. The whole system is designed to compute programmable models and connectivity schemes.