Unless the speed gap between CPU and memory disappears, efficient memory usage remains a decisive factor for performance. To optimize data usage of programs in the presence of the memory hierarchy, we are particularly interested in two compiler techniques: pool allocation and field layout restructuring . Since foreseeing runtime behaviors of programs at compile time is difficult, most of the previous work relied on profiling. On the contrary, our goal is to develop a fully automatic compiler that statically transforms input codes to use memory efficiently. Noticing that regular expressions , which denote repetition explicitly, are sufficient for memory access patterns, we describe how to extract memory access patterns as regular expressions in detail. Based on static patterns presented in regular expressions, we apply pool allocation to repeatedly accessed structures and exploit field layout restructuring according to field affinity relations of chosen structures. To make a scalable framework, we devise and apply new abstraction techniques, which build and interpret access patterns for the whole programs in a bottom-up fashion. We implement our analyses and transformations with the CIL compiler. To verify the effect and scalability of our scheme, we examine 17 benchmarks including 2 SPECINT 2000 benchmarks whose source lines of code are larger than 10,000. Our experiments demonstrate that the static layout transformations for dynamic memory can reduce L1D cache misses by 16% and execution times by 14% on average.

In many computer systems with large data computations, the delay of memory access is one of the major performance bottlenecks. In this paper, we propose an enhanced field remapping scheme for dynamically allocated structures in order to provide better locality than conventional field lay outs. Our proposed scheme reduces cache miss rates drastically by aggregating and grouping fields from multiple instances of the same structure, which implies the performance improvement and power reduction. Our methodology will become more important in the design space exploration, especially as the embedded systems for data oriented application become prevalent. Experimental results show that average L1 and L2 data cache misses are reduced by 23% and 17%, respectively. Due to the enhanced localities, our remapping achieves 13% faster execution time on average than original programs. It also reduces power consumption by 18% for data cache.

This paper presents a new approach to the synthesis of parallel multiplier circuits with an objective of minimizing leakage power consumption under circuit timing constraint. Our leakage power optimization is based on the use of dual-threshold voltage (Vt) technology. From experiments using a set of benchmark designs, it is shown that the approach is quite effective.

In deep submicrometer (DSM) design, the interconnect delay becomes equally as or more important than that of logic gates. In particular, to achieve timing closure in DSM design, it is essential to consider the interconnect delay at an early stage of the synthesis process. Unfortunately, few successes of achieving a tight link of front-end synthesis to back-end layout have been reported, from a practical point of view, mainly due to the inaccuracy of predicting the layout effects during the synthesis. In this brief, we address a new approach to the problem of synthesis of parallel multiplier circuits combined with the consideration of layout effects. The approach is intended to overcome some of the limitations of the previous works, in which the effects of layout on the synthesis have either not been taken into account or considered only in local and limited ways, or the computation time is extremely large. The proposed approach refines the structure and placement of the circuit by iteratively performing two tasks. Task 1: timing-driven relocation. For a parallel multiplier circuit that was restructured at the prior iteration, we attempt to replace the modules in the structure while retaining the interconnects to find a placement with shorter timing. Task 2: timing-driven resynthesis. We attempt to restructure the interconnect topology of the placement obtained from Task 1 to further reduce the circuit timing, employing two heuristics: a modified version of timing-optimal FA-tree allocation by Stelling et al. (1996), considering interconnect delay, and a critical path-based local interconnect refinement. The iterative mechanism of the two tasks practically tightly integrates the synthesis and placement tasks so that both of the effects of placement on the results of synthesis and the effects of synthesis on the results of placement are taken into account. From experiments using a set of benchmark designs, it is shown that the approach is quite effective and efficient, producing designs with less interconnect delay over the sequential method of synthesis and placement.