With exacerbated DRAM read disturbance, transparent in-DRAM defenses require space (to track the aggressor rows) and time (to perform more mitigations). To reduce storage overhead, recent works have developed probabilistic row-sampling techniques with several entries. To address the time issue, these techniques employ Refresh Management (RFM) commands introduced in DDR5. However, probabilistic defenses with RFM face two critical challenges: (i) fixed-probability sampling under dynamic activation patterns can cause row-sampling misses, allowing attacks to evade mitigation, and (ii) RFM causes timing variations that can be exploited for side and covert channels to leak sensitive information. The goal of this paper is to design a low-cost and secure in-DRAM defense that overcomes these challenges.

Solid state drives (SSDs) based on NAND flash technology are steadily gaining popularity and mass market adoption due to their increased storage capacity and density. However, because of the more bits in each cell and the reduced cell spacing, they are experiencing a decline in reliability. The most efficient way to ensure reliability of data is to use low-density parity-check (LDPC) codes. Nevertheless, using a hybrid decoding technique for LDPC codes results in a significant decoding latency, which exacerbates performance issues. In this paper, we propose a variable-dimensional LDPC coding scheme, called VDLDPC, to reduce the high decoding latency and thus improve read performance of NAND flash memory on hot read data. One of the crucial designs in the VDLDPC scheme is the two-dimensional LDPC (TD-LDPC) algorithm. TD-LDPC implements row and column encoding separately when writing data to the flash memory by using sub-LDPC codes. Errors in the data arise after a period of retention. When the data is read out, TD-LDPC performs row and column decoding using sub-LDPC codes, and the column decoding result can be re-decoded as a new round of row decoding input. Simulation results show that the proposed VDLDPC scheme has the advantage in decoding latency and reduces the flash memory read response time by up to 12.0% (5.8% on average across all workloads) compared to the current LDPC code scheme. The proposed VDLDPC scheme ensures reliability while improving NAND flash system read performance on hot read data.

NAND flash memory employs high code rate low-density parity-check (LDPC) codes to reduce the amount of redundant data that must be added. When the code rate is high, although the redundancy space is small, the error correction capability is inferior to medium or low code rate LDPC. RBER varies among the storage layers for 3D triple-level cell (TLC) NAND flash memory, which increases the frequency of read retry operations. Repeatedly initiating read retry seriously increases the decoding latency and decreases the performance of the 3D TLC NAND flash memory. To alleviate this problem, this article proposes Intra-Layer Variation aware LDPC coding, called LVLDPC. The proposed LVLDPC scheme establishes the correlation between inter-layer interference and raw bit error rate (RBER) based on a neural network model. By analyzing and predicting RBER through the neural network model, we are able to categorize RBER into distinct levels. Then, we then select LDPC codes with appropriate error correction capabilities to decode data with varying levels of RBER. Through this scheme, we don’t need to start read retry when RBER <1.56×10-2. The iteration number is reduced by 67% in total. This scheme only causes 1.15% space overhead, which is negligible. For the stage with high RBER, the number of iterations of LVLDPC is still large, and the extended LVLDPC scheme (eLVLDPC) is further proposed to reduce the use of high code rate and reduce the number of iterations by 19.1%, expanding the correctable RBER threshold to 2.68×10-2.

Through stacking and multi-bit technology, three-dimensional (3D) flash memory enhances storage capacity and density; nevertheless, the reduction in noise margin results in an increase in raw bit error rate (RBER) and a decrease in data reliability. Low-density parity-check (LDPC) codes are widely used in flash memory for improving data reliability because of its strong error correction capability. In the early stages of 3D flash memory use, the RBER is low, and hard decision decoding (e.g., bit flipping decoding) is generally invoked for error correction. Existing LDPC codes with dynamic threshold bit flipping (DTBF) decoding algorithms cannot correct bit errors when the gradually increasing RBER exceeds its error correction threshold, resulting in an increase in decoding latency. To enhance error correction capability and reduce decoding latency, this paper proposes SiDTBF: merging soft information with DTBF LDPC decoding for 3D NAND flash memory. First, the read reference voltage of various interval lengths is applied in accordance with the threshold voltage distribution drift characteristics of the 3D flash memory cell to get the decoding soft information of each bit. Second, the strong and weak bits are distinguished using the soft information. In contrast to weak bits, which are more likely to be erroneous, strong bits are more likely to be correct. Finally, all the strong and weak bits are input as initial values for bit-flip iterative decoding. Using the column weight of the parity-check matrix, the threshold for the number of flipped weak bits is determined in the first decoding iteration process. The portion of the weak bits that exceeds the threshold is flipped. In the ensuing iteration phase, the DTBF decoding algorithm is used. SiDTBF improves decoding error correction performance by fusing each bit’s soft information with the DTBF algorithm during the decoding phase. Simulation results show that compared with current DTBF, SiDTBF significantly improves bit flipping decoding error correction capability and reduces decoding latency.

3D NAND flash memory is currently the mainstream storage medium due to high density and large capacity. However, the high raw bit error rate (RBER) poses challenges to data reliability. Low-density parity-check (LDPC) codes, known for strong error correction capabilities, are widely used to ensure data reliability. Traditional error correction schemes employ a single, fixed LDPC code, resulting in suboptimal performance–excess decoding overhead at low RBER and insufficient correction capability at high RBER. To address these limitations, we propose DyLDPC: a dynamic LDPC code with variable correction capability to improve decoding performance for 3D NAND flash memory. DyLDPC dynamically adjusts the error correction capability of LDPC codes based on the temporal and spatial variations of RBER in 3D NAND flash memory. Temporally, RBER increases with retention time and program/erase (P/E) cycles. Spatially, RBER varies across layers and pages. DyLDPC predicts RBER under varying conditions and allocates appropriate LDPC codes accordingly, effectively reducing ECC storage overhead, extending flash memory lifespan, and improving decoding efficiency. While ensuring data reliability, it optimizes error correction performance. Evaluations indicate that DyLDPC reduces decoding iterations by 8.1% and latency by 74% on average compared to static schemes. Additionally, using differentiated LDPC codes for most significant bit (MSB) and least significant bit (LSB) pages in multi-level cell (MLC) NAND further reduces LSB decoding latency by 27.8%.

In the age of artificial intelligence, large language models (LLM) require rapid development along with massive volumes of training data and parameter storage. Over the past decade, 3D NAND flash memory has emerged as the dominant non-volatile memory technology due to its high bit density and large capacity. However, because of its 3D vertical stacking technique and array designs, 3D NAND flash memory has more complicated data loss mechanisms compared to 2D NAND flash memory. As bit densities rise to Quad-level-cells (QLC), the small read margins will further complicate and make the situation more unpredictable. In this work, we propose an error-bit prediction model in this paper for 3D QLC NAND flash memory with the charge-trap (CT) cell structure based on a thorough analysis of multiple parameters that affect the error-bit distributions, including read disturb (RD) and degradation from program/erase (PE) cycles. Specifically, we develop the whole-block prediction (WBP) and the dynamic-worst-page prediction (DWPM) models. It is shown that the proposed models can be used for high-precision error-bit prediction to guarantee data reliability in commonly used NAND-based storage systems based on the characterization results of raw NAND chips.

Reliability challenges like random telegraph noise (RTN) and intercell electrostatic interference have gotten worse as feature sizes in planarnandflash memory continue to reduce. In order to improve storage capacity, 3-D stacking ofnandflash memory has emerged as the preferred development path. However, additional challenges are brought about by the switch to 3-Dnandflash, such as shorter lifespans and lower reliability as a result of higher integration densities and intricate vertical interference. This article proposes RaPC: a raw bit error rate (RBER) aware polar coding scheme for improving data reliability of 3-Dnandflash memory. According to the variation of the RBER, the error correction ability of the polar code is dynamically adjusted to correct bit errors, which ensures the reliability and reduces the decoding delay. Simulation results demonstrate that RaPC offers significant advantages in decoding latency and performance over conventional low-density parity-check (LDPC) codes within specific RBER ranges, making it a promising solution for enhancing the reliability of 3-Dnandflash memory.

Three-dimensional (3D) NAND flash memory has become quite popular and is now widely used in data centers and mobile devices due to its outstanding storage density and cost-effectiveness. Larger storage capacity is made possible by 3D quad-level cell (QLC) NAND flash memory with the charge-trap (CT) structure, which stores four bits in each cell. However, data reliability is sacrificed in exchange for greater capacity. The lifespan of data retention is crucial for non-volatile storage. Thus, an important role is played by the Arrhenius model, which is widely used for lifespan prediction and high-temperature acceleration testing. Interestingly, we discover that the conventional Arrhenius model is inaccurate after analyzing the data retention properties of 3D QLC NAND flash memory. An empirical model is proposed for changing the apparent activation energy (Ea) based on the influence of different parameters, in order to accurately predict data lifespan and perform accelerated experiments. This developed model provides a temperature-and cycle-related parameter table for Ea, which is useful for high-temperature acceleration testing examinations. Simultaneously, we observe a linear connection between the 40∘C data retention time mapping and the other temperatures. We evaluate the effects of the modified Ea model and the classic Arrhenius model with the epitaxial data and conclude that the former can reduce the error by approximately 70% to a maximum.

NAND flash memory employs high code rate low-density parity-check (LDPC) code to minimize redundant data. High code rates reduce redundancy but compromise error cor-rection compared to medium/low code rates. Raw bit error rate (RBER) varies among the storage layers for 3D triple-level cell (TLC) NAND flash memory, which causes the number of using read retry to increase. Repeatedly initiating read retry seriously increases the decoding latency and decreases the performance of the 3D TLC NAND flash memory. To alleviate this problem, this article proposes Intra-Layer Variation aware LDPC coding, called LVLDPC. The LVLDPC scheme categorizes RBER into distinct levels. Then, we select LDPC codes with appropriate error correction capabilities to decode data with varying levels of RBER. Through this scheme, we don't need to start read-retry when RBER$< 1.56\times 10^{-2}$. The iteration number is reduced by 67% in total. This scheme only causes 1.15 % space overhead, which is negliaible,

Dynamic random access memory (DRAM) is being upgraded iteratively, and as a result, its transmission rate and bandwidth are rising quickly. Simultaneously, as the DRAM process has advanced, the storage cell size has decreased and cell integration has improved within each device, leading to a significant boost in storage capacity and density. DRAM has been widely utilized as a crucial storage component in personal computers, mobile devices, servers, and data centers because of these benefits. However, data reliability is greatly hampered by DRAM’s vulnerability to single-bit, row, and column errors, which result in data loss and corruption as well as the possibility of system crashes and downtime. Error correction codes (ECC) are used by DRAM to protect data and increase reliability, but because large capacity DRAM is more prone to multi-bit errors of cross-chip. Traditional error correction strategies are unable to keep up with the demand for multi-bit errors of cross-chip. Therefore, a crucial problem that needs to be solved is the design of an ECC strategy with robust error correction capabilities. A high order ECC scheme with stronger error correcting capability is developed at a higher firmware layer without changing the hardware architecture to address reliability issues brought by DRAM multi-bit errors of cross-chip. The higher order ECC technique is then used to gain a stronger error correction capability while minimizing the latency overhead when an uncorrectable error is discovered by rank-level ECC (RECC). The error correction performance of the proposed high order ECC algorithm is evaluated and verified using simulation experiments in terms of both error correction capability and encoding/decoding latency. Simulation results show that compared with existing ECC schemes, the proposed high order ECC scheme for DRAM reduces latency by 69% and storage overhead by 5.56%. The proposed high order ECC method has significant research implications and is useful in preventing data loss and enhancing DRAM reliability.

3-D NAND flash memory is the ubiquitous nonvolatile memory (NVM) on the market because of its large storage capacities, high reliability, and low bit cost. The reliability characteristics of 3-D NAND flash memory, however, are considerably different from those of 2-D NAND flash memory due to the peculiar architectures. In this article, read disturb (RD) at various program/erase (P/E) stages is thoroughly explored. To adjust the low-density parity check (LDPC) codes dynamically and extend the lifetime of 3-D NAND flash memory, short-term lifetime prediction models of RD and endurance are proposed based on in-depth studies on the correlations of fail bit count (FBC) at various lifetime stages, and their accuracy is tested experimentally. A new short-term warning system (STWS) is proposed to extend the lifetime of 3-D NAND-based storages. It consists of the error-bits’ prediction module (EBPM) and the self-adjustable LDPC codes module (SLDPC), where EBPM predicts FBC periodically and SLDPC preallocates LDPC codes for future use based on the result of EBPM. The experimental result shows that our prediction models have high reliability, and STWS can effectively prolong the lifetime of NAND flash. The findings of this study provide fundamental insights into FBC degradation in 3-D NAND flash, as well as a simple and practical method for building 3-D NAND-based storage with high reliability.

Low-density parity-check (LDPC) codes have been widely adopted to guarantee data reliability in 3-D NAND flash memory. However, the iterative LDPC decoding algorithm leads to high-decoding latency due to the iterative message transfer mechanism. Using a field-programmable gate array (FPGA) testbed, we first present the binary channel in NAND flash and analyze the single-symbol log-likelihood ratio (LLR) variation with the decoding iterations. Subsequently, we investigate the raw bit error ratio (RBER) characteristics of intrapage frames. To reduce the number of iterative decoding, we propose a frame feedback information aware decoding algorithm (FFIA-DA), combined with the single-symbol LLR variation and the similar error characteristics among intrapage frames. The proposed method uses the decoding feedback information of one frame to decrease the number of decoding iterations of other frames with similar RBER. Experiments show that the proposed approach can improve the decoding performance of LDPC and speed up decoding convergence.

Low read latency, long lifetime, and high storage density have all been demonstrated in phase-change memory (PCM), making it an attractive contender for main memory. However, due to resistance drift per cell caused by long-term storage, data reliability becomes a major challenge. Low-density parity-check (LDPC) codes with improved error correction capability can be used in PCM to reduce bit error rates and thus improve data reliability. More interestingly, when the raw bit error rates (RBERs) of various pages in PCM is compared at the same storage time, a considerable gap appears, resulting in high sensing and decoding latency. We propose eLDPC, an efficient LDPC coding scheme for reducing sensing and decoding latency, in this article. We start with a preliminary experiment, which reveals that there is a significant variation in resistance drifts between adjacent distributions, resulting in a large RBER gap for different pages. Then, using a submatrix of the parity-check matrix to shorten the codeword length, eLDPC is inspired to encode pages with lower RBER. The original bit sequence is separated into even bit sequence (EBS) and odd bit sequence (OBS) for pages with higher RBER. eLDPC is used to encode EBS and OBS independently. By utilizing optimized soft information, EBS and OBS are eLDPC decoded. eLDPC can significantly improve the error correction capability of LDPC hard decoding, effectively eliminating soft decoding processes, and lowering decoding latency. The results of simulations show that eLDPC can greatly decrease decoding iterations and time.

In this paper, read disturb (RD) at various program/erase (P/E) stages has been thoroughly explored, and short-term lifetime prediction models of RD and endurance are proposed. Based on these, a new short-term warning system (STWS) is proposed, which can extend the lifetime of 3D NAND-based storage by adjusting LDPC codes dynamically. The experimental result shows that the proposed prediction models have high reliabilities, and STWS can effectively prolong the lifetime of NAND flash.

3-D NAND flash memory with vertically stacked layers has been widely applied benefiting from its large capacities and high performances. Recently, a novel open block operation scheme was proposed for further improvements of the utilization efficiency in large capacity blocks. In this article, reliability issues of the open block operation in 3-D charge-trap (CT) NAND flash memory are studied by focusing on the high raw bit error rates (RBERs) in the last programmed word-line (WL), which is named as the edge WL (EWL). By systematical characterizations, it is concluded that high RBER in the EWL originates from lateral charge migration (LCM) due to the special structure of 3-D CT NAND flash. To suppress the RBER in EWL, we propose the extra read (ER) and extra program (EP) schemes to compensate for the charge loss from LCM. The experimental results show that the RBER of EWL can be reduced by an average of 59.8% and 86.5% after adopting ER and EP schemes, respectively. Furthermore, for the highly reliable open block, we design a targeted low-density parity-check (LDPC) operation process to enhance the correction capability. By using these two methods, experimental results show that the error correction capabilities of the LDPC hard decoding are increased by 1.92 and 4.76 times, respectively.

Low-density parity-check (LDPC) codes have been widely adopted in NAND flash in recent years to enhance data reliability. There are two types of decoding, hard-decision and soft-decision decoding. However, for the two types, their error correction capability degrades due to inaccurate log-likelihood ratio (LLR) . To improve the LLR accuracy of LDPC decoding, this article proposes LLR optimization schemes, which can be utilized for both hard-decision and soft-decision decoding. First, we build a threshold voltage distribution model for 3D floating gate (FG) triple level cell (TLC) NAND flash. Then, by exploiting the model, we introduce a scheme to quantize LLR during hard-decision and soft-decision decoding. And by amplifying a portion of small LLRs, which is essential in the layer min-sum decoder, more precise LLR can be obtained. For hard-decision decoding, the proposed new modes can significantly improve the decoder’s error correction capability compared with traditional solutions. Soft-decision decoding starts when hard-decision decoding fails. For this part, we study the influence of the reference voltage arrangement of LLR calculation and apply the quantization scheme. The simulation shows that the proposed approach can reduce frame error rate (FER) for several orders of magnitude.

Solid-state drive (SSD) gradually dominates in the high-performance storage scenarios. Three-dimension (3D) NAND flash memory owning high-storage capacity is becoming a mainstream storage component of SSD. However, the interferences of the new 3D charge-trap (CT) NAND flash are getting unprecedentedly complicated, yielding to many problems regarding reliability and performance. Alleviating these problems needs to understand the characteristics of 3D CT NAND flash memory deeply. To facilitate such understanding, in this article, we delve into characterizing the performance, reliability, and threshold voltage ( V th ) distribution of 3D CT NAND flash memory. We make a summary of these characteristics with multiple interferences and variations and give several new insights and a characterization methodology. Especially, we characterize the skewed ( V th ) distribution, ( V th ) shift laws, and the exclusive layer variation in 3D NAND flash memory. The characterization is the backbone of designing more reliable and efficient flash-based storage solutions.

3D NAND flash memory faces unprecedented complicated interference than planar NAND flash memory, resulting in more concern regarding reliability and performance. Stronger error correction code (ECC) and adaptive reading strategies are proposed to improve the reliability and performance taking a threshold voltage (Vth) distribution model as the backbone. However, the existing modeling methods are challenged to develop such a Vthdistribution model for 3D NAND flash memory. To facilitate it, in this paper, we propose a machine learning-based modeling method. It employs a neural network taking advantage of the existing modeling methods and fully considers multiple interferences and variations in 3D NAND flash memory. Compared with state-of-the-art models, evaluations demonstrate it is more accurate and efficient for predicting Vthdistribution.

3-D NAND flash memory is gradually being widely used in solid state drives (SSDs), leading to increasing storage capacity. However, the read performance of SSD is sacrificed for decoding operations which are executed to guarantee the data reliability. No matter whether the data have bit errors, they will be sent to error correcting code (ECC) engine to decode, introducing a high read delay of SSD. Error prechecking can help to avoid the redundant decoding operations for the error-free data, but it induces extra checking overhead to the error data. Motivated by this, we carry out comprehensive experiments to analyze the distribution of bit errors in 3-D NAND flash memory. The preliminary experimental results show that there are a large number of pages read without errors in the early lifetime of 3-D NAND flash memory. Based on the observations and analyses, we propose a model to estimate the error-free ratio, and utilize it to design a dynamic error prechecking scheme (DEPS) to bypass the decoding operation for the error-free data in 3-D NAND flash memory and improve the read performance of SSD. Furthermore, by dividing a large page into small subpages, DEPS releases more error-free data, which significantly improves the read performance of SSD. Evaluation results from real-world traces demonstrate that by implementing DEPS, the average read performance of SSD is enhanced by 35%-55% with 3-D MLC NAND flash memory.

Three-dimensional (3D) NAND flash memory has high capacity and cell storage density by using the multi-bit technology and vertical stack architecture, but degrading data reliability due to high raw bit error rates (RBER) caused by program/erase (P/E) cycles and retention periods. Low-density parity-check (LDPC) codes become more popular error-correcting technologies to improve data reliability due to strong error correction capability, but introducing more decoding iterations at higher RBER. To reduce decoding iterations, this paper proposes BeLDPC: bit errors aware adaptive rate LDPC codes for 3D triple-level cell (TLC) NAND flash memory. Firstly, bit error characteristics in 3D charge trap TLC NAND flash memory are studied on a real FPGA testing platform, including asymmetric bit flipping and temporal locality of bit errors. Then, based on these characteristics, a high-efficiency LDPC code is designed. Experimental results show BeLDPC can reduce decoding iterations under different P/E cycles and retention periods.

3-D NAND flash memory has been attracting much attention owing to its ultrahigh storage density and low bit cost, and it has been widely applied in data centers and mobiles. 3-D triple-level-cell (TLC) NAND flash memory can achieve much larger storage capacity by storing 3 bits in each cell. However, the data reliability issues induced by data retention (DR) and read disturb (RD) greatly limit 3-D TLC NAND applications in hot data storage where the stored data are frequently accessed and RD is more serious. In this article, we first systematically study the retention correlated RD (RCRD) errors in 3-D charge trap (CT) TLC NAND flash memory under various conditions. Error characteristics and underlying mechanisms much different from 2-D NAND flash memory are observed: 1) for RCRD with short retention-after data program, error bits increase due to the negative-shift of program states and 2) for RCRD with long retention-after retention 12 h, error bits can be partially recovered on the contrary due to the charge compensation. We propose schemes of precharge the storage layer (PCSL) and thermally stabilize the storage layer (TSSL) to improve the reliability of 3-D NAND flash memory. By using these two methods, experimental results show that raw bit error rates (RBERs) can be significantly reduced by 30% and 20%, respectively.

3-D triple-level cell (3-D TLC) NAND flash has high storage density and capacity, but degrading data reliability due to high raw bit error rates induced by a certain number of program/erase cycles. To guarantee data reliability, low-density parity-check (LDPC) codes are selected as the error correction codes in modern flash memories because of strong error correction capability. However, directly adopting LDPC codes induces high decoding latency due to iterative updating of log-likelihood ratio (LLR) information in the decoding process. Increasing LLR information accuracy can greatly improve decoding performance. In this paper, we propose EMAL: using error modes aware LDPC codes for further enhancing the decoding performance of 3-D TLC NAND flash. We first obtain 3-D TLC error modes based on an FPGA testing platform, and then exploit the error modes to optimize LLR information and enable the decoding to converge at a high speed. The simulation results show that the decoding performance is significantly improved, resulting in reduced bit error rates and decoding latency.

Existing studies have uncovered that there exist significant Raw Bit Error Rates (RBERs) variations among different layers of 3D flash memories due to manufacture process variation. These RBER variations would cause significantly diversed read latencies when reading data with traditional Low-Density Parity-Check (LDPC) codes designed for planar flash memories, which induces sub-optimal read performance of flash-based Solid-State Drives (SSDs).

3D charge trap (CT) triple-level cell (TLC) NAND flash gradually becomes a mainstream storage component due to high storage capacity and performance, but introducing a concern about reliability. Fault tolerance and data management schemes are capable of improving reliability. Designing a more efficient solution, however, needs to understand the reliability characteristics of 3D CT TLC NAND flash. To facilitate such understanding, by exploiting a real-world testing platform, we investigate the reliability characteristics including the raw bit error rate (RBER) and the threshold voltage (Vth) shifting features after suffering from variable disturbances. We give analyses of why these characteristics exist in 3D CT TLC NAND flash. We hope these observations can guide the designers to propose high efficient solutions to the reliability problem.

Low-density parity-check (LDPC) codes have been widely adopted in NAND flash in recent years to improve data reliability. However, their error-correction capability degrades due to inaccurate log-likelihood ratio (LLR). To improve LLR accuracy of LDPC decoding, this paper proposes a threshold voltage distribution aware LLR optimization scheme, called VaLLR. Firstly, we build a threshold voltage distribution model for 3D triple-level cell (TLC) NAND flash. Then, by exploiting the model, we introduce the VaLLR scheme to quantize LLR during soft-decision decoding. And by amplifying a portion of small LLRs, which is essential in the layer minsum decoder, more precise LLR can be obtained. Finally, we study the influence of the reference voltage arrangement on LLR calculation and apply the VaLLR scheme during decoding. The simulation shows that the proposed approach can improve the FER performance for several orders of magnitude.

By storing multibit per cell, multilevel cell (MLC) NAND flash memory achieves high storage capacity, but sacrificing data reliability. Error correction codes, such as Bose–Chaudhuri–Hocquenghem (BCH) codes, are widely used to ensure data reliability. However, high raw bit error rates induced by interference noises make BCH codes become insufficient to guarantee data reliability. Low-density parity-check (LDPC) codes are considered as the replacement due to the stronger error correction capability. Nevertheless, directly exploiting LDPC codes introduces a concern about decoding latency because of their iterative decoding in the soft decision process. To develop effective LDPC decoding algorithms, it is necessary to have a more profound understanding on flash failure patterns. This paper first observes the pair-bit errors (PBEs) characteristic of MLC NAND flash memory on a real field-programmable gate array testing platform, then proposes a PBE-aware LDPC (PAL) decoding scheme-based upon this observation, in which PBE provides the promotion information for LDPC decoding to reduce decoding latency. Simulation results show that the decoding latency can be reduced by up to 54%, compared with the conventional LDPC codes.

NAND flash memory has decreasing storage reliability, as the density or program/erase (P/E) cycle increases. To ensure data integrity, error correction codes (ECCs) are widely employed and typically stored in the out-of-band area (OOB) of flash pages. However, the worst-case oriented ECC is largely under-utilized in the early stage (small P/E cycles), and the required ECC redundancy may be too large to fit in OOB in the late stage (high P/E cycles). In this paper, we propose LAE-FTL, which employs a lifetime-adaptive ECC scheme, to improve the performance and lifetime of NAND flash memory. LAE-FTL uses weak ECCs in the early stage and strong ECCs in the late stage to guarantee the storage reliability. Since OOB is large enough to store weak ECCs in the early stage, small and size-incremental codewords are adaptively used to improve data transfer and decoding parallelism. In the late stage, strong ECCs have to be employed and the ECC redundancies become too large to be stored in OOB. Thus, LAE-FTL stores the exceeding ECC redundancies in the data space of flash pages and stores user data in a cross-page fashion. Finally, our trace-driven simulation results show that LAE-FTL improves the read performance by up to 63.42%, compared to the worst-case oriented ECC scheme in the early stage, and significantly improve the storage reliability at low cost in the late stage.

With the improvement of flash memory storage density, data reliability and flash lifetime are decreased. Error correction codes (ECC) and error management schemes can boost both reliability and lifetime. However, in order to develop effective fault tolerance algorithms and management solutions, it is very necessary to have a more profound understanding of failure modes of flash memory. To enable such understanding, we design an experimental platform and scheme to clearly investigate flash failure modes. This paper examines various failure modes occurring at 2x-nm MLC NAND flash technologies, such as page allocation scheme-based program interference (PASBPI) errors (i.e., different page allocation schemes mean data can be programmed into flash pages in different ways, which can lead to different program interference errors), write errors of the least significant bit (LSB) and the most significant bit (MSB) and different data pattern-based read interference errors (i.e., different data values programmed into flash pages can cause differential read interference errors). We analyze these observed failure modes and explain why they exist. We hope it is helpful to understand these discovered failure modes to propose effective fault tolerance and error management algorithms.

The storage capacity of NAND Flash has increased by scaling down to smaller cell size and using multi-level storage technology, but data reliability is degraded by severer retention errors. To ensure data reliability, error correction codes (ECC) are adopted, such as BCH and low-density parity check (LDPC) codes. However, BCH codes are insufficient when raw bit error rates (RBER) caused by retention errors are high. As a result, BCH codes are inevitably replaced with LDPC codes with stronger error correction capability. Traditional LDPC codes are used to independently correct bit errors in the LSB and MSB pages. Unfortunately, decoding latency in such two pages is significantly unbalanced, MSB pages take much higher latency due to higher RBER, leading to suboptimal flash read performance. This paper proposes a cooperative error correction scheme, called CooECC, to reduce LDPC decoding latency of the MSB page in NAND Flash. By exploiting data error characteristics introduced by retention errors, CooECC integrates the decoding result of the LSB page into the initial information of LDPC decoding for the MSB page, making it more accurate. This in turn enables decoding to converge at a higher rate. Simulation results show that for LDPC schemes with information lengths of 2KB and 4KB, the decoding latency can be reduced by up to 87% and 84%, respectively, when RBER is as high as 8.0 × 10^-3.

By scaling down to smaller cell size, NAND flash has significantly increased the storage capacity in order to lower the unit cost down. However, the reliability is sacrificed due to much higher raw bit error rates. As a result, conventional error correction codes (ECCs), such as BCH codes, are not sufficient. Low-density parity check (LDPC) codes with stronger error correction capability are adopted in NAND flash to guarantee data reliability. However, read performance using LDPC is poor because of its decoding complexity. It has been found that flash cells with fewer electrons are more prone to program interference errors. As a result, program interference errors show the characteristic of value dependence. This characteristic can be exploited and translated into extra information facilitating the decoding convergence. Motivated by this observation, we propose PEAL: a flash program interference error aware LDPC scheme to enhance the decoding performance. PEAL integrates the obtained extra information from the value dependence into the soft-to-hard decision process in LDPC decoding to decrease decoding iterations and improve the decoding convergence speed. Simulation results show that decoding iterations are reduced by up to 69.37% and the decoding convergence speed is improved by up to 2.5×, compared with the normalized min-sum (NMS) algorithm with 2KB information lengths at an approximate raw bit error rate of 11.5 × 10 −3 .

Continuous technology scaling makes NAND flash cells much denser. As a result, NAND flash is becoming more prone to various interference errors. Due to the hardware circuit design mechanisms of NAND flash, retention errors have been recognized as the most dominant errors, which affect the data reliability and flash lifetime. Furthermore, after experiencing a large number of programm/erase (P/E) cycles, flash memory would suffer a much higher error rate, rendering traditional ECC codes (typically BCH codes) insufficient to ensure data reliability. Therefore, low density parity check (LDPC) codes with stronger error correction capability are used in NAND flash-based storage devices. However, directly using LDPC codes with belief propagation (BP) decoding algorithm introduces non-trivial overhead of decoding latency and hence significantly degrades the read performance of NAND flash. It has been observed that flash retention errors show the so-called numerical-correlation characteristic (i.e., the 0-1 bits stored in the flash cell affect each other with the leakage of the charge) in each flash cell. In this paper, motivated by the observed characteristic, we propose REAL: a retention error aware LDPC decoding scheme to improve NAND flash read performance. The developed REAL scheme incorporates the numerical-correlation characteristic of retention errors into the process of LDPC decoding, and leverages the characteristic as additional bits decision information to improve its error correction capabilities and decrease the decoding latency. Our simulation results show that the proposed REAL scheme can reduce the LDPC decoding latency by 26.44% and 33.05%, compared with the Logarithm Domain Min-Sum (LD-MS) and Probability Domain BP (PD-BP) schemes, respectively.

As NAND flash memory chips become denser, they are more vulnerable to random errors caused by ageing, read or write interference, and erase operations. These errors compromise both the data integrity and lifetime of flash memory so that error correction codes (ECC) are employed by the flash controller to strengthen the fault tolerance. The BCH (Bose Chaudhuri Hochquenghem) code is a widely used ECC technique in flash-based storage devices due to its strong error correction capability and high performance. The third step of decoding a BCH code is the Chien search process, which locates the errors in the received codeword. To increase the decoding throughput, parallel Chien search algorithms are used, but existing algorithms occupy more than 60% area of the total decoding logic, increasing the hardware complexity and energy consumption. To reduce the hardware complexity and overhead, in this paper, we propose a plane optimization algorithm to reduce the redundant XOR gates used in the Chien search process. Our study based on intensive experiments shows that for a (2047,1926, 11) BCH code with the parallel factor of 32, the proposed optimization algorithm reduces the number of XOR gates used in the Chien search process by 79%, 46% and 13%, respectively, compared to the straightforward implementation, the GMA approach and the strength-reduced architecture.