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Meng Zhang 0017

dblp:04/6901-17 · DBLP profile ↗
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4ranked-venue papers
2as first author
0since 2021 · last 2014
—ORCID · conflict

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 4 · 2 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
4 papers
Electronic design automation · 51% Memory systems · 22% Energy-efficient computing · 20%

Topics — the 6 heaviest of 7, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › hardware verification and test
hardware verification
0.632014
PVCoherence: Designing flat coherence protocols for scalable verification · HPCA 2014
Scalably verifiable dynamic power management · HPCA 2014
Architecting Dynamic Power Management to be Formally Verifiable · DAC 2014
Energy-efficient computing › power management
dynamic power management
0.422014
Scalably verifiable dynamic power management · HPCA 2014
Architecting Dynamic Power Management to be Formally Verifiable · DAC 2014
Electronic design automation › hardware verification and test
formal verification
0.422014
Scalably verifiable dynamic power management · HPCA 2014
Architecting Dynamic Power Management to be Formally Verifiable · DAC 2014
Memory systems
cache coherence
0.322014
PVCoherence: Designing flat coherence protocols for scalable verification · HPCA 2014
Fractal Coherence: Scalably Verifiable Cache Coherence · MICRO 2010
Memory systems › cache coherence › cache coherence protocol
cache coherence protocol verification
0.112010
Fractal Coherence: Scalably Verifiable Cache Coherence · MICRO 2010
Processor architecture and microarchitecture
chip multiprocessor
0.112014
Scalably verifiable dynamic power management · HPCA 2014

Methods — techniques the papers use, named apart from their topics

formal verification · 0.4simulation · 0.2parametric verification · 0.2fractal design methodology · 0.1automated formal tools · 0.1
YearPublicationVenuePosition
2014 Architecting Dynamic Power Management to be Formally Verifiable
abstract
Many computer systems employ dynamic power management (DPM) to maximize power efficiency. DPM offers great opportunities, but deploying it carries significant risks if the DPM scheme is not completely verified. We propose architecting the DPM scheme such that it can be formally verified regardless of the size of the system.
Daniel J. Sorin, Opeoluwa Matthews, Meng Zhang 0017
DAC3
2014 Scalably verifiable dynamic power management
abstract
Dynamic power management (DPM) is critical to maximizing the performance of systems ranging from multicore processors to datacenters. However, one formidable challenge with DPM schemes is verifying that the DPM schemes are correct as the number of computational resources scales up. In this paper, we develop a DPM scheme such that it is scalably verifiable with fully automated formal tools. The key to the design is that the DPM scheme has fractal behavior; that is, it behaves the same at every scale. We show that the fractal design enables scalable formal verification and simulation shows that our scheme does not sacrifice much performance compared to an oracle DPM scheme that optimally allocates power to computational resources. We implement our scheme in a 2-socket 16-core x86 system and experimentally evaluate it.
Opeoluwa Matthews, Meng Zhang 0017, Daniel J. Sorin
HPCA2
2014 PVCoherence: Designing flat coherence protocols for scalable verification
abstract
The goal of this work is to design cache coherence protocols with many cores that can be verified with state-of-the-art automated verification methodologies. In particular, we focus on flat (non-hierarchical) coherence protocols, and we use a mostly-automated methodology based on parametric verification (PV). We propose several design guidelines that architects should follow if they want to design protocols that can be parametrically verified. We experimentally evaluate performance, storage overhead, and scalability of a protocol verified with PV compared to a highly optimized protocol that cannot be verified with PV.
Meng Zhang 0017, Jesse D. Bingham, John Erickson, Daniel J. Sorin
HPCA1
2010 Fractal Coherence: Scalably Verifiable Cache Coherence
abstract
We propose an architectural design methodology for designing formally verifiable cache coherence protocols, called Fractal Coherence. Properly designed to be fractal in behavior, the proposed family of cache coherence protocols can be formally verified correct for systems with an arbitrary number of cores, using existing, automated formal tools. We show, by designing and implementing a specific Fractal Coherence protocol, called Tree Fractal, that Fractal Coherence protocols can attain comparable performance to traditional snooping and directory protocols.
Meng Zhang 0017, Alvin R. Lebeck, Daniel J. Sorin
MICRO1