No trouble found (NTF) due to functional failures is a common scenario today in board-level testing at system companies. A component on a board fails during the board-level functional test, but it passes the automatic test equipment (ATE) test when it is returned to the supplier for warranty replacement or service repair. To find the root cause of NTF, we propose an innovative functional test approach and discrete Fourier transform (DFT) methods for the detection of board-level functional failures. These DFT and test methods allow us to reproduce and detect functional failures in a controlled deterministic environment, and provide ATE tests to the supplier for early screening of defective parts. Experiments on an industry design show that the proposed functional scan test with appropriate functional constraints can adequately mimic the functional state space, as measured by appropriate coverage metrics. Experiments also show that most functional failures due to dominant bridging, crosstalk, and delay faults due to power supply noise can be reproduced and detected by functional scan test. We also describe two approaches to enhance the mimicking of the functional state space. The first approach allows us to select a given number of initial states in linear time and functional scan tests resulting from these selected states are used to mimic the functional state space. The second approach is based on controlled state injection.

Despite recent advances in structural test methods, the diagnosis of the root cause of board-level failures for functional tests remains a major challenge. A promising approach to address this problem is to carry out fault diagnosis in two phases-suspect faulty components on the board or modules within components (together referred to as blocks in this paper) are first identified and ranked, and then fine-grained diagnosis is used to target the suspect blocks in a ranked order. We propose a new method based on dataflow analysis and Dempster-Shafer (DS) theory for ranking faulty blocks in the first phase of diagnosis. The proposed approach transforms the information derived from one functional test failure into multiple-stage failures by partitioning the given functional test into multiple stages. A measure of “belief” is then assigned to each block based on the knowledge of each failing stage, and the DS theory is subsequently used to aggregate the beliefs from multiple failing stages. Blocks with higher beliefs are ranked on the top of the candidate list. Simulations on an industry design for a network interface application as well as on an open source system-on-a-chip show that the proposed method can provide accurate ranking for most board-level functional failures.

We propose output deviations as a surrogate metric to grade functional test sequences at the register-transfer level without explicit fault simulation. Experimental results for the open-source Biquad filter core and the Scheduler module of the Illinois Verilog Model show that the deviations metric is computationally efficient and it correlates well with gate-level coverage for stuck-at, transition-delay and bridging faults. Results also show that functional test sequences reordered based on output deviations provide steeper gate-level fault coverage ramp-up compared to other ordering methods.

A common scenario in industry today is “No Trouble Found” (NTF) due to functional failures. A component on a board fails during board-level functional test, but it passes the Automatic Test Equipment (ATE) test when it is returned to the supplier for warranty replacement or service repair. To find the root cause of NTF, we propose an innovative functional test approach and DFT methods for the detection of boardlevel functional failures. These DFT and test methods allow us to reproduce and detect functional failures in a controlled deterministic environment, which can provide ATE tests to the supplier for early screening of defective parts. Experiments on an industry design show that functional scan test with appropriate functional constraints can adequately mimic the functional state space well (measured by appropriate coverage metrics). Experiments also show that most functional failures due to stuck-at, dominant bridging, and crosstalk faults can be reproduced and detected by functional scan test.

Despite recent advances in structural test methods, the diagnosis of the root cause of board-level failures for functional tests remains a major challenge. A promising approach to address this problem is to carry out fault diagnosis in two phases -- suspect faulty components on the board or modules within components (together referred to as blocks in this paper) are first identified and ranked, and then fine-grained diagnosis is used to target the suspect blocks in ranked order. We propose a new method based on dataflow analysis and Dempster-Shafer theory for ranking faulty blocks in the first phase of diagnosis. The proposed approach transforms the information derived from one functional test failure into multiple-stage failures by partitioning the given functional test into multiple stages. A measure of "belief" is then assigned to each block based on the knowledge of each failing stage, and Dempster-Shafer theory is subsequently used to aggregate the beliefs from multiple failing stages. Blocks with higher beliefs are ranked at the top of the candidate list. Simulations on an industry design for a network interface application show that the proposed method can provide accurate ranking for most board-level functional failures.

A common scenario in industry today is “No Trouble Found” (NTF) due to functional failures. A component on a board fails during board-level functional test, but it passes the Automatic Test Equipment (ATE) test when it is returned to the supplier for warranty replacement or service repair. To find the root cause of NTF, we define an innovative deterministic test, namely functional scan test. We also propose two approaches for using functional scan test to adequately mimic functional state space. The first approach allows us to select a given number of initial states in linear time and functional scan tests resulting from these selected states are used to mimic the functional state space effectively. The second approach adopts a state-injection technique. Experiments on an industry design show that by using either multiple initial states or state injection, functional scan test with appropriate functional constraints can mimic the functional state space well, measured by appropriate coverage metrics. Therefore, it is feasible to use functional scan test to detect board-level functional failures in a controlled deterministic environment and diagnose the root cause to faulty wires/gates inside a component. It is also shown that the proposed method outperforms a random method in selecting the given number of effective initial states.

We present a design-for-testability (DFT) technique for increasing the effectiveness of LFSR reseeding for unmodeled defects. The proposed method relies on seed selection using the output-deviations metric and the on-chip augmentation of seeds using simple bit-operations. Simulation results for benchmark circuits show that compared to LFSR reseeding using output deviations alone, the proposed method provides higher coverage for transition-delay and bridging faults, and steeper coverage ramp-up for these faults for the same number of seeds. For the same pattern count (and much fewer seeds), the proposed method provides comparable unmodeled defect coverage. In all cases, complete coverage of modeled stuck-at faults is obtained. We therefore conclude that high test quality can be obtained with the proposed LFSR reseeding method using a smaller number of seeds.

Functional test sequences are often used in manufacturing testing to target defects that are not detected by structural test. Therefore, it is necessary to evaluate the quality of functional test sequences. However, it is very time-consuming to evaluate the quality of functional test sequences by gate-level fault simulation. Therefore, we propose output deviations as a metric to grade functional test sequences at the register transfer (RT)-level without explicit fault simulation. Experimental results for the open-source Parwan processor and the Scheduler module of the Illinois Verilog Model (IVM) show that the deviations metric is computationally efficient and it correlates well with gate-level coverage for stuck-at, transition-delay, and bridging faults. Results also show that functional test sequences that are reordered based on output deviations provide steeper gate-level fault coverage ramp-up compared to other ordering methods.

Linear feedback shift register (LFSR) reseeding forms the basis for many test-compression solutions. A seed can be computed for each test cube by solving a system of linear equations based on the feedback polynomial of the LFSR. Despite the availability of numerous LFSR-reseeding-based compression methods in the literature, relatively little is known about the effectiveness of these seeds for unmodeled defects, particularly since there are often several candidate seeds for a test cube. We use the recently proposed output deviation measure of the resulting patterns as a metric to select appropriate LFSR seeds. Experimental results are reported using test patterns for stuck-at and transition faults derived from selected seeds for the ISCAS-89 and the IWLS-05 benchmark circuits. These patterns achieve higher coverage for transition and stuck-open faults than patterns obtained using other seed-generation methods for LFSR reseeding. Given a pattern pair (p1,p2) for transition faults, we also examine the transition-fault coverage for launch on capture by usingp1andp2to separately compute output deviations. Results show thatp1tends to be better when there is a high proportion of do-not-care bits in the test cubes, whilep2is a more appropriate choice when the transition-fault coverage is high.