We address the problem of survivable path pair routing in multi- domain optical networks with geographically correlated failures. The objective is to minimize the risk of simultaneous failure of both the primary and backup paths. We develop a probabilistic model to calculate the simultaneous failure probability of both the paths and consider a topology aggregation scheme for domains based on calculating the physical vulnerable overlapping area of two paths within a domain. We develop an inter-domain minimum overlapping area routing algorithm based on the aggregated information from each domain. We compare our algorithm to Suurballe's Algorithm and an optimal approach and we show that our heuristic approach is effective in reducing the total probability of simultaneous failure.

In this paper, we present a database management scheme for an intelligent surveillance system utilizing multiple visual sensors and RFID readers. The objects are tracked and identified by multiple visual sensors and RFID readers. We define three different types of data structure to consistently store data for effective data storage. They contain global object number and identification as the common information of the same object. The global object number is uniquely assigned for each track object. The previously stored data without the common information is back-annotated when it is available in the system. Moreover, when the global object number changes because of imperfect detection and tracking, the system maintains consistency information between global object numbers for the same object by comparing their local target information or positions. The fragmented information for an object is also stitched through map information. The simulation results demonstrate that the database information for objects is successfully recovered with consistency.

We consider virtual optical network (VON) provisioning over a flexible-grid multi-domain optical network with the objective of minimizing total network cost, including the cost of transponders, regenerators, and spectrum. We propose a three-step heuristic algorithm that addresses the issues of domain selection, topology aggregation, and routing, modulation format, and spectrum assignment (RMSA) when mapping virtual optical links onto multi-domain physical optical links. We propose a domain selection technique that attempts to minimize the number of inter- domain virtual optical links. We then suggest a topology aggregation (TA) technique to exchange intra and inter-domain information between domains, and propose a method for RMSA over the aggregated topology. Numerical results show that our heuristic approach is effective in reducing total network cost.

We consider survivable virtual network mapping in a multi-domain optical network with the objective of minimizing total network link cost for a given virtual traffic demand that is embedded over the multi-domain optical network. The survivability constraint guarantees the connectivity of virtual nodes after any single optical link failure. We propose a hierarchical software-defined networking (H-SDN)-based control plane to exchange information between domains, and we propose heuristic approaches for mapping virtual links onto multi-domain optical links using partition and contraction mechanisms (PCM) on the virtual topology. We show that the proposed PCM technique can reduce time complexity compared to traditional cut set graph theory approaches. Numerical results show that our heuristic approach is effective in reducing total network cost and increasing the successful mapping rate.

We consider the problem of efficient virtual optical network (VON) mapping in a multi-domain optical network (VON-MD) with the objective of minimizing total network link cost for a given VON demand that is embedded over the multi-domain optical network. Topology aggregation (TA) is used to exchange intra and inter-domain information between domains, and heuristic algorithms are proposed for embedding considering different domain selection techniques and virtual link ordering techniques. We provide an integer linear programming formulation (ILP-VON-MD) to compare with our heuristic approaches. Numerical results show that our heuristic approaches are effective in reducing total network cost.

In this paper, we present the design and implementation of a general, flexible, hardware-aware network platform that takes hardware processing behavior into consideration to accurately evaluate network performance. The platform adopts a network-hardware co-simulation approach in which the NS-2 network simulator supervises the network-wide traffic flow and the SystemC hardware simulator simulates the underlying hardware processing in network nodes. In addition, as a case study, we implemented wireless all-to-all broadcasting with network coding on the platform. We analyze the hardware processing behavior during the algorithm execution and evaluate the overall performance of the algorithm. Our experimental results demonstrate that hardware processing can have a significant impact on the algorithm performance and hence should be taken into consideration in the algorithm design. We expect that this hardware-aware platform will become a very useful tool for more accurate network simulations and more efficient design space exploration of processing-intensive applications.

This paper presents a methodology for reducing interconnect resources in reconfigurable platforms such as field-programmable gate arrays (FPGAs). This methodology utilizes the techniques developed for the buffer-based dataflow, a new design representation suitable for implementing data-centric applications in a reconfigurable platform. In a buffer-based dataflow, nodes correspond to processing blocks and buffer controllers represent the interconnects between the processing blocks. Since we can isolate the functional execution and data transfer of each node by using buffer controllers, a buffer-based dataflow is helpful for reducing overall design time and for increasing reconfigurability. In this paper, we propose a sharing methodology that can reduce the buffer memory and the number of buses used in the realization of a buffer-based dataflow. By reducing the resources allocated to buffer controllers, we can achieve interconnect resource reduction. The proposed sharing methodology can increase the dynamic energy consumption due to the increased port-loading capacitance. By using the energy consumption model determined by the costs of buffers and buses, we investigate whether the sharing case with the minimum resources corresponds to the sharing case consuming the minimum energy or not. We evaluate the proposed sharing methodology with the dataflow graphs representing data-centric applications such as SIRF, IPv4, MC-CDMA transmitter and receiver.

This paper presents an effective design methodology which maps a complex system represented as a dataflow graph to a reconfigurable target architecture having multi-core processors and programmable logics. In order to synchronize data transfers between two processing blocks mapped to different processors (alternatively, one block is mapped to a processor and the other is realized as a hardware), we propose a mapping methodology that exploits the buffer-based dataflow, a new representation technique for realizing data-centric applications in reconfigurable platforms. From the buffer-based dataflow and estimated execution times of functional blocks and data transfers, the proposed methodology creates a mapped partition and generates the template code which runs on the processors of the target platform. We also use a processor initiation scheme to prevent wrong operations from happening when actual execution takes longer than estimated. Our proposed mapping methodology and the generated template code are evaluated with the SystemC model and Xilinx ISE.

This paper presents a map based robot navigation and localization algorithm using laser range finder for indoor environments. A navigation path is given by the sequence of grids and global map information is represented by the list of vertexes. The grid based navigation facilities path planning as well as complements localization with priori information of the grid sequence. The pattern of vertexes is represented by distance, adjacency, and slant among them for the comparison between map information and range data. A mobile robot is globally localized by finding the matched pattern between the set of vertexes from the map and the set of vertexes from the range data. The proposed method is verified with actual range data from laser range finder.

We address a new inherent limitation of potential field methods, which is symmetrically aligned robot-obstacle-goal (SAROG). The SAROG involves one critical risk of local minima trap. For dealing with the problem, we investigate the way how the local minima trap is recognized, and present our random force algorithm. The force algorithm has two categories of random unit total force (RUTF) and random unit total force with repulsion removal (RUTF-RR) which are selected based on the conditions of a robot, an obstacle and a goal.

In this paper, we present the design and implementation of a general, flexible hardware-aware network platform which takes hardware processing behavior into consideration to accurately evaluate network performance. The platform adopts a network-hardware co-simulation which the NS-2 network simulator supervises the network-wide traffic flow and the SystemC hardware simulator simulates the underlying hardware processing in network nodes. In addition, as a case study, we implemented wireless all-to-all broadcasting with network coding on the platform. processing behavior during the algorithm execution and evaluate the overall performance of the algorithm. Our experimental results demonstrate that hardware processing has a significant impact on the algorithm performance and hence should be taken into consideration in the algorithm design. We expect that this hardware-aware platform will become a very useful tool for more accurate network simulations and optimal designs of processing-intensive applications.

Due to proliferation of diverse network applications, DoS/DDoS attacks are evolving. Many studies have been performed and implemented in on/off-line network devices such as routers and IDS/IPS. While IDS/IPS is powerful enough to handle deep packet inspection (DPI) tasks, routers are better suited in real-time and line-speed processing requirements. Since the routers are designed to handle IP packet header information, if one can devise an DoS/DDoS detection/prevention methods that utilizes the router specific features it will be best for the in-line and real-time processing. We introduce a Flow based DoS/DDoS detection algorithm(FDDA) that detects Distributed Denial of Service (DDoS) attacks by monitoring TTL and ID fields of incoming packet's IP header. As DDoS attacks are based on IP source address spoofing, the TTL and ID fields may have abnormal behavior. The device keeps track of 8-tuple flow table. The behavior of these two fields is monitored to determine DoS/DDoS attack situation. The effectiveness of our method is such that it is implemented flow-based routers and devices.

In this paper, we present an approach for providing dynamic object association and identification in heterogeneous sensor networks where identification sensors have coverage uncertainty. Detection uncertainty of identifications by the coverage uncertainty is managed by grouping unassociated identifications. In the system, visual sensors find corresponding objects between cameras by using homographic lines and track them by using multi-camera localization scheme. Identification sensors (i.e., RFID system, fingerprint or iris recognition system) are incorporated into the tracking system for objects identification. This paper elaborates possible identification cases and necessary conditions with the coverage uncertainty of identification sensors. Finally, the proposed association method is evaluated with a realistic simulation.

Object detection by visual sensors is a critical component of surveillance systems and has many challenging issues. This paper addresses enhancement of object detection with multiple visual sensors. The detection enhancement we introduce is to recover missed object detection given partially detected objects among multiple visual sensors. Once an object is detected by one or more visual sensors, the detected local object positions are transformed into a global object position. Based on a local and global collaboration, any missed local object position is recovered by the global to local transformation. However, the collaboration may degrade the detection performance by incorrectly recovering the local object position, which is propagated from false object detection. Furthermore, local object positions corresponding to an identical object are transformed into in equivalent global object positions due to detection uncertainty such as a shadow. In this paper, we minimize the performance degradation by preventing from the propagation of the false object detection. In addition, we present an evaluation method for a final global object position. Finally, the proposed method is analyzed and evaluated with case studies.

Multiple object association is an important capability in visual surveillance system with multiple cameras. An association approach using the limits of field of View (FOV) of cameras is well accepted but this approach has to wait until the object crosses the limits for association. Also, FOV information has to be determined whenever the setup of camera is changed. Our approach is to dynamically generate the global homographic line whenever it is needed for multi-object association with the aim to work on dynamic camera environment, where the change of camera frequently occurs and objects move in a complicated fashion. We show that, with this approach, the system can initiate association procedure as needed and allow itself to actively adapt to the dynamic environment, while maintaining consistent states of the objects.

This paper develops and evaluates the threshold based algorithm proposed in [1] for dynamic data association in wireless sensor networks. The sensor node incorporates RFID reader and acoustic sensor where the signals are fused for tracking and associating multiple objects. The RFID tag is used for object identification and acoustic sensor is used for estimating object movement. For the better data association, we apply the particle filtering for the prediction of an object. The algorithm with the particle filtering has an effect on increasing the association case where even objects overlap. The simulation result is compared to that using only the original algorithm. The association performance under single node coverage and multiple node coverage is evaluated as a function of sampling time.

This paper addresses the problem of 3-dimensional (3D) multitarget tracking using particle filter with the joint multitarget probability density (JMPD) technique. The estimation allows the nonlinear target motion with unlabeled measurement association as well as non-Gaussian target state densities. In addition, we decompose the 3D formulation into multiple 2D particle filters that operate on the 2D planes. Both selection and combining of the 2D particle filters for 3D tracking are presented and discussed. Finally, we analyze the tracking and association performance of the proposed approach especially in the cases of multitarget crossing and overlapping.

This paper initially shows ROHC and packet aggregation significantly improve the number of successful voice calls. However, the improvement does not include processor's processing overhead, which is identified by measuring ROHC processing time from Intel Pentium 4 and RouterBOARD, and applying the results into NS-2 simulations. Simulation results indicate the number of successful voice calls is seriously affected by the processing overhead. For the solution of the processing limitation, we propose a hardware model of the two algorithms and numerically analyze the model. Simulation results show the hardware model makes the number of successful voice calls approach the ideal (no-delay) case, and the numerical model exactly characterizes the hardware behaviors.

This paper proposes objects tracking method by association with RFID and visual sensors. The detection from RFID readers with proximity to each object results in coarse localization. The estimation is determined by a virtual sensor which is comprised of RFID readers detection combination. Each virtual sensor has a reference point which represents the center of possible positions. After the coarse estimation, image frames from two cameras improve the estimation close to a real position based on parallel projection model. The visual compensation sufficiently accomplishes the refined tracking. The experimental results show our proposed algorithm remarkably accomplishes the localization performance.

Wireless Mesh Network (WMN) supports various types of mesh clients such as sensor networks, cellular; 802.11/e Wireless LAN, etc. In this case, it needs to be suitably organized and adopt well-known or newly proposed algorithm to guarantee high and reliable mesh performance. This paper applies RObust Header Compression (ROHC) originate from cellular data network plus packet aggregation to WMNs when mesh clients generate small-size fusion data, i.e., sensor (delivered by UDP) and voice over IP (VOIP) data. We preliminarily analyze ROHC and packet aggregation improve UDP throughput and the number of supported voice calls. However; the improvement does not include a processor's processing overhead for ROHC and packet aggregation, which is examined by measuring ROHC execution time from Intel Pentium 4 and RouterBOARD, and applying the results into NS-2 simulations. The results indicate UDP and voice performance are seriously affected by the processing overhead. As a solution for the performance degradation, we introduce a hardware design for the two algorithms. By using SystemC Hardware Description Language (HDL), we first design hardware specification composed of 1Ghz master clock and 333Mhz BUS system. Then, we integrate the hardware model into previous NS-2 network model, and propose profile-based network/hardware co-simulation method which gives insight how to investigate real-timing characteristics of the hardware model in the view of network behaviors.

In this paper, we present a hardware architecture for a Sampling Importance Resampling Filter (SIRF) applied to systems with multiple interacting models. This filter outperforms traditional filters in practical scenarios due to superior abilities of the SIRFs in dealing with nonlinear and/or non-Gaussian models. Compared to existing approaches, our method does not require knowledge of model transition probabilities and keeps a constant number of particles per model at all times. This allows for a regular hardware structure with deterministic execution time. A highly scalable, parallel architecture consisting of distributed processing elements and a central unit is described. We propose an interconnection scheme and data exchange protocol using the concept of distributed resampling that greatly speeds up filter execution and drastically reduces the required interconnect to a single bus without causing any communication bottleneck. The proposed architecture is evaluated on a Xilinx FPGA platform for a multiple model target tracking application and its efficiency and scalability is shown.

In most multitarget tracking approaches based on joint probabilistic data association (JPDA), it is difficult to apply the solutions to problems (due to the dimensionality curse of heavy complexity) where the number of target varies dramatically. In this paper, we introduce an algorithm for detection of multitargets in wireless acoustic sensor networks (ADMAN); we localize detected targets by particle filtering after ADMAN. The purpose of ADMAN is detecting any number of targets (We know the approximate locations of targets during the detection algorithm.) in the field of interest. The advantage of ADMAN is its ability to cope with varying number of targets in time. ADMAN does not have any restrictions on the varying pattern of the target number

Performance in multihop wireless networks is known to degrade with the number of hops for both TCP and UDP traffic. For VoIP, the wireless network presents additional challenges as the perceived quality is dependent on loss, delay and jitter. Furthermore, small size of VoIP packets aggravates network utilization of the 802.11 based wireless mesh network. In this work, we evaluate the packet aggregation algorithms to reduce VoIP protocol overhead, compare the aggregation algorithms and propose a distributed packet aggregation mechanism. The experimental results demonstrates that the proposed distributed packet aggregation algorithm improves the VoIP quality and results in significant increase in the number high quality VoIP calls supported over multihop mesh.

Assured forwarding per-hop behavior (AF PHB) is a forwarding scheme for providing QoS in DiffServ networks. It defines four classes and three drop precedence, where buffer space and bandwidth are defined as forwarding resources for each AF class (J. Heinanen et al., 1999). RIO (D.D. Clark and W. Fang, 1998) could be used as drop policy in a DiffServ router. AF PHB could be implemented by WRR, WFQ, CBQ, etc. When network managers provide AF PHB using the scheduling mechanisms, they want to guarantee accurate achievement of service expectation level, which results from precise queue weight allocation to each AF class with respect to forwarding resources, i.e., buffer space and bandwidth. In order to provide a guideline for the precise queue weight allocation, this paper proposes a simple analytical model for AF PHB designed on RIO and M/M/1 queue, and uses this model to obtain queue weight equation (QWE), which performs fine calculation of queue weight for AF classes. Average buffer space and bandwidth allocated for each AF class are used in derivation of QWE. The model verification is performed by simulation in which we use WRR for simplicity. Simulation results show that the QWE supports an accurate allocation of the forwarding resources, and, as a result, makes four AF classes achieve fairness as well as service expectation levels

In this work, we focus on increasing network utilization to support real-time applications, especially voice over IP, in 802.11b wireless mesh network. For increasing capacity, we investigate on two directions: use of packet aggregation and utilize of header compression. Although aggregation reduces 802.11 MAC overhead, it also increases delay. We present a distributed multihop aggregation algorithm that uses the "natural" waiting time in the interface queue of packets in a loaded network. Header compression can relax the VoIP protocol overhead, but it also introduces the signaling overhead. In our work, we propose a zero-length header compression algorithm integrated with packet aggregation, which doesn't need to depend on the signaling mechanism to recover the context discrepancy between compressor and decompressor. The above performance optimization techniques are experimented in the NS2 simulator. The experimental results show an increase of 12 times for a six hop string when all optimizations are used

In the recent past, there has been a tremendous increase in the popularity of VoIP services as a result of huge growth in broadband access. The same voice-over-Internet protocol (VoIP) service poses new challenges when deployed over a wireless mesh network, while enabling users to make voice calls using WiFi phones. Packet losses and delay due to interference in a multiple-hop mesh network with limited capacity can significantly degrade the end-to-end VoIP call quality. In this work, we discuss the basic requirements for efficient deployment of VoIP services over a mesh network. We present and evaluate practical optimizing techniques that can enhance the network capacity, maintain the VoIP quality and handle user mobility efficiently. Extensive experiments conducted on a real testbed and ns-2 provide insights into the performance issues and demonstrate the level of improvement that can be obtained by the proposed techniques. Specifically, we find that packet aggregation along with header compression can increase the number of supported VoIP calls in a multihop network by 2-3 times. The proposed fast path switching is highly effective in maintaining the VoIP quality. Our fast handoff scheme achieves almost negligible disruption during calls to roaming clients

This paper presents a flexible 2/spl times/2 matrix multiplier architecture. The architecture is based on word-width decomposition for flexible but high-speed operation. The elements in the matrices are successively decomposed so that a set of small multipliers and simple adders are used to generate partial results, which are combined to generate the final results. An energy reduction mechanism is incorporated in the architecture to minimize the power dissipation due to unnecessary switching of logic. Two types of decomposition schemes are discussed, which support 2's complement inputs, and its overall functionality is verified and designed with a field-programmable gate array (FPGA). The architecture can be easily extended to a reconfigurable matrix multiplier. We provide results on performance of the proposed architecture from FPGA post-synthesis results. We summarize design factors influencing the overall execution speed and complexity.

This paper presents a reconfigurable platform for executing data centric applications. The proposed platform realizes applications where buffers are dominated in the design. Such characteristics of application domain is mostly exhibited by loop based processing systems. To increase the throughput, the platform is centered around buffers interacting through reconfigurable interconnect. Each buffer is associated with an autonomous reconfigurable controller where reconfiguration parameters are obtained statically from the dataflow graph. The execution concurrency is maintained by two level pipelining mechanism. We illustrate that the proposed platform is highly regular and decreases dynamic reconfiguration time significantly.

A novel low-complexity residual resampling scheme for particle filters is presented. The proposed scheme uses a simple but effective "particle-tagging" method to compensate for a possible error that can be caused by finite-precision quantization in the resampling step of particle filtering. The scheme guarantees that the number of particles after resampling is always equal to the number of particles before resampling. The resulting scheme is suitable for high-speed physical realization when the number of particles is a power of two.

Resampling is a critically important operation in the implementation of particle filtering. In parallel hardware implementations, resampling becomes a bottleneck due to its sequential nature and the increased complexity it imposes on the traffic of the designed interconnection network. To circumvent some of these difficulties, we propose two new resampling algorithms. The first one, called residual-systematic resampling, combines the merits of both systematic and residual resampling and is suitable for pipelined implementation. It also guarantees the fixed duration of the resampling procedure irrespective of the weight distribution of the particles. The second algorithm, referred to as partial resampling, has low complexity and reduces traffic load through the hardware network. These two algorithms should also be considered as resampling methods in simulations on standard computers.