In this paper we are proposing a new system for the production of VR stories that allow users seamless interaction with the content. Our system plays real life footage rather than animation allowing for interactive live-action experiences. The unaware empowered users take subliminal decisions by focusing their attention at predefined ROIs. The moment a decision is taken is always placed seconds before the actual video branching happens to allow the system to preload only the chosen storyline in order to keep the computational workload as low as possible. We believe that this unique system will not only change the way we experience VR contents, but will rather lead to a paradigm shift in film production.

UPDATED---31 October 2015. This paper discusses an educational game for kindergarten children to encourage collaboration between them. A game (Tata N Taro Adventure) was designed for children from 4 to 6 years old to encourage collaborations between children in remote and local environments. For this purpose, two classrooms are connected via the Internet. The game content was designed to include multiple gameplays to support a variety of collaboration types. Kinect was used as the interaction device for children. The game was developed using unity game engine. The effectiveness of the game for encouraging collaboration was examined by observing children's engagement levels and interactions from the viewpoints of the collaboration scheme, game structure, and the usage of the Kinect. The experiments were conducted at 3 kindergartens with 38 children participating in total. The results show that with the proposed game design, children gained motivation to interact more with their peers and to compete healthily with each other.

Pervasive computing allows immediate image and sound capturing, interaction with content, participation in content productions, and thus virtually anyone can become a multimedia content producer on the spot. With our research focus on collaborative content production, we designed a platform called "Poligatari" which aims at bringing professional content producers and amateur filmmakers together.

This JSAC special issue is covering four emerging areas in communications: Area 1 - e-Health; Area 2 - Peer-to-Peer Networking; Area 3 - Vehicular Networks and Telematics Applications; and Area 4 - Social Networks. This is the first issue of a brand new series in JSAC focusing on "Emerging Technologies in Communications." These emerging technical areas were selected from ComSoc's Technical Committees and Technical Sub-Committees. (The second issue will be published later in 2013 on the following areas: Area 5 - Applications of Nanotechnologies in Communications; Area 6 - Autonomic Communications; Area 7 - Fiber Wireless Integration; and Area 8 - Nanoscale and Molecular Networking.) The papers selected are briefly summarized. For this issue, 55 regular papers were selected for publication out of 197 open-call submissions. Also included are three overview (invited) papers. It is devoted to reporting on cutting-edge research achievements covering the following four emerging technical areas in communications.

This paper discusses a new approach to efficient system design verification that uses an FPGA based real-time emulator. The architecture of a real-time emulator suitable for high-speed digital transmission system emulation and an experimental system are described. The proposed system consists of an emulation engine using the custom designed multi-chip module FPGA called PROTEUS-MCM, a program control unit, and a physical interface. The system can be used not only for real-time emulation of high-speed transmission systems, but also as initial systems for actual communication networks.

The paper discusses a new architecture for reconfigurable real time signal transport systems that uses FPGAs and describes an experimental system design. The basic architecture of the reconfigurable transport system is proposed based on the requirements for real time signal transport in a typical telecommunication network. The proposed system consists of reconfigurable modules using the custom designed FPGA called PROTEUS, a program control module for hardware/software coprocessing, and line interface modules including an automatic connection control mechanism. The system can be used not only for the initial installation stages of actual communication systems, but also for rapid prototyping tools or emulators.

A new FPGA (Field Programmable Gate Array) is developed for high-speed digital telecommunication systems. As architecture is based on the fundamental characteristics extracted from an analysis of actual systems. The FPGA has several unique features for realizing high-speed transport data processing. It allows us to build the high-performance components that are frequently used in transport data processing. In addition, its inter-chip connection mechanism enables us to build flexible multi-FPGA modules. Furthermore, we introduce a dedicated CAD system for the FPGA. We design several actual transport processing circuits on the FPGA using the CAD system and evaluate them. Experimental results show that the device has the potential to realize practical systems.

This paper presents a new technique for improving the performance of a synchronous circuit configured as a look-up table based FPGA without changing the initial circuit configuration; only the register location is altered. It improves clock speed and data throughput at the expense of latency. One of the most significant benefits realized by this approach is that the time-consuming and user-uncontrollable reconfiguration processes, i.e., remapping, replacement, and rerouting, are unnecessary when improving circuit performance. After applying our technique to some benchmark circuits, the average performance improvement was 33% for six combinational circuits, and 25% for 18 sequential circuits.>

This paper discusses a new architecture for programmable hardware targeted at high-speed digital telecommunication systems and describes a preliminary design. The basic architecture of the programmable hardware is proposed based on the characteristics of functions and an analysis of logic used in actual communication subsystems performing high-speed bit level operations. The proposed architecture, called PROTEUS, includes a pipeline structure of logic and latch groups, and a 2-stage logic block structure that consists of small LUTs and wide gates. The design strategy of a prototype chip and the CAD techniques used to achieve the required performance are also discussed.>

A multicomputer-type parallel processing system has been developed that offers a peak performance of 12.8 GFLOPS. This system is called NOVI-II HiPIPE, and was designed for super-high-definition (SHD) image processing. SHD image is a new image medium and its resolution is higher than that of HDTV. Because SHD image processing requires computing power that exceeds the ability of any single digital signal processor (DSP), current or anticipated, NOVI-II HiPIPE uses a multicomputer-type parallel processing architecture. A 100-MFLOPS vector processor serves as the backend processor of each processing element. The current version of NOVI-II HiPIPE uses 128 mesh connected processing elements and 128 vector processors. The configuration and performance of NOVI-II HiPIPE are described.>

The VLSI design of a one-chip vector processor (VP) for parallel digital signal processing (DSP) systems is described. The VP aims at a peak performance of 100 MFLOPS (32-b) for typical digital signal processing applications. To achieve this performance based on existing CMOS technology, a very-long-instruction-word-type pipeline architecture was used. The pipeline processing architecture and the functional units configuration are shown. A high-level behavioral-description-based CAD system called PARTHENON was used to design the functions and logic circuits of VP. The suitability and effectiveness of PARTHENON for the VP design are shown in terms of parallel operation and pipeline-stage description. The estimated work load in the VP design with PARTHENON is one order of magnitude smaller compared to conventional CAD tools.>

This paper discusses the bit-rate compression of super high definition images with Discrete Cosine Transform (DCT). Super high definition images with more than 2048x2048 pixels of resolution are introduced as the next generation image category beyond HDTV. In order to develop bit-rate reduction algorithms, an image I/O system for super high definition still images is assembled. A traditional DCT based coding algorithm called Scene Adaptive Coder (SAC) is applied to super high definition images and related problems are clarified. A new coding algorithm is proposed, which takes human visual perception characteristics into consideration, and its coding performance is examined for super high definition images.

A novel audio coding scheme is presented for the transmission of music signals with about 20 kHz bandwidth in asynchronous-transfer-mode-based networks. The coding algorithm is based on subband division and embedded ADPCM (adaptive differential pulse-code modulation) techniques in order to minimize the quality degradation by packet loss and to meet the various service grade demands on performance. The advantages of the proposed algorithm are investigated theoretically and compared to those of conventional embedded ADPCM. The SNR improvements are computed using actual radio signals. Rate control strategies are briefly discussed in case of packet loss.>

This paper describes the architecture and performance of a massively parallel computer system for “Digital Signal Processing” called NOVI-II. The computer will have a peak arithmetic rate of 50 GFLOPS and 1.024 Gbyte of memory. NOVI-II is intended mainly for the video signal processing of high quality moving pictures, and for developing programs for a programmable video CODEC. NOVI-II adopts multicomputer-type architecture which allows the combination of more than 512 processing elements(PEs). In each PE, a Transputer(T800) is used as a CPU, along with a vector processor, 2MB external RAM and a Parallel Program Development Assistant (PDA) probe fabricated on two gate arrays. Its PDA system facilitates powerful debugging functions to observe all program states. Optical links and optical networks are introduced to provide stable and flexible communications between PEs. The expected performance of the system with a large grain scheduling technique for real-time video processing is also discussed.

Basic characteristics of variable-rate video coders applied to asynchronous transfer mode (ATM) transmission are described. Burstiness of video information is evaluated for conference-type scenes using various coding algorithms. Three measures (distribution, autocorrelation, and coefficient of variation) are introduced to evaluate burstiness. Video sources are modeled and characterized by the autoregressive process and coefficient of variation. Video quality improvement achieved with variable rate transmission is evaluated using signal-to-noise ratio (SNR) and subjective ratings. An improvement of 5-10 dB in temporal SNR and 1 rank in mean opinion score are reported.>

To extract full performance from a multicomputer digital signal processing (DSP) system, the development of a viable load balancing technique is considered indispensable. The authors describe a task allocation and control methodology for image signal processing, such as is used in a low-bit rate (e.g. 64-kb/s) motion picture coding system. On a massive homogeneous multicomputer-type DSP system, the following approaches increase system performance substantially: (1) task scheduling with interframe prediction; (2) layered large-grain data flow; and (3) predefined local reassignment of processing. The effects of these various methods are examined in the context of a low bit rate motion picture codec with motion compensation and vector quantization application.>

The authors introduce a parallel DSP (digital signal processing) system called NOVI, consisting of 36 processor nodes. NOVI has a multicomputer architecture, which provides high programmability and effective scheduling capability. Its program-development-assist system facilitates powerful debugging functions to observe all states of NOVI and to control its execution. Each processor node comprises a transputer, a floating-point ALU (arithmetic logic unit), and 1 Mbyte of local memory, which can deal with even rather large tasks within a single node. An interconnection board allows easy reconfiguration into various network topologies.>

This paper describes a 32kbit/s adaptive delta modulation (ADM) CODEC which can be applied to digital portable telephones. This ADM CODEC employs a new adaptation algorithm and parameters adjusted for speech signals. The encoding algorithm makes it possible to achieve higher quality with the 32 kbit/s ADM CODEC than with 6 bit µ-law PCM coding. The developed ADM CODEC including a coder, a decoder and switched-capacitor filters on a chip can operate on a single power supply(3.6∼ 5V). The power dissipation is only 30 mW during normal operation and less than 10 mW in the power-down mode. The CMOS chip is an a 16-pin package, 7 × 4.3mm.