This paper proposes a novel noise-shaping (NS) successive approximation register (SAR) based light-to-digital converter (LDC) for continuous multi-wavelength (MW) photoplethysmogram (PPG) monitoring. The proposed NS-SAR LDC employs a single-channel current-integration (CI) SAR quantizer with a three-channel passive NS loop filter performs time-multiplexed, low-power NS readout for MWPPG. The cascade integrator feedforward NS architecture features a passive nested feedback path, which contributes one additional NS order. The LDC enables a wide dynamic range (DR) through the high signal-to-noise-and-distortion ratio (SNDR), inherent AC gain control of the proposed CI NS-SAR, and a predictive threshold filter that compensates for large DC and drifting baseline currents induced by motion artifacts and interference light. Fabricated in a 180-nm standard CMOS process, the NS-SAR LDC consumes$26.5~\mu $W while achieving a SNDR of 95 dB and a total DR of 161.5 dB. The work is validated through finger MWPPG measurements using commercial PPG sensors.

This article presents a hybrid third-order continuous-time delta–sigma modulator (CT DSM) with a 5-MHz bandwidth, tailored for low-power applications. The design is facilitated by a passive pole-optimized second-order noise-shaping successive-approximation register (NS SAR) quantizer. A sampling–settling-merged technique is proposed with the assistance of a canceling conductance output stage, leading to significantly suppressed sampling errors and an extension of the available time budget for the NS SAR quantizer. The technique merges the NS SAR quantizer’s sampling phase with the settling phase of the integration of the continuous-time (CT) feedback digital-to-analog converter (DAC), achieving a power-efficient integration and sampling process. This approach relaxes the operational transconductance amplifier (OTA) requirements in the CT loop and enhances both the resolution and power efficiency of the DSM. The NS SAR quantizer, featuring left-half-circle (LHC) poles, enables complex conjugate poles optimization for the noise transfer function, enabling an excess loop delay compensation (ELDC)-free design. Fabricated in a 65-nm CMOS process, the prototype analog-to-digital converter achieves a 71.6-dB signal-to-noise and distortion ratio within the 5-MHz bandwidth at an oversampling ratio of 20. The design consumes 0.6 mW of power, achieving a Schreier figure of merit (FoM) of 170.8 dB and Walden FoM of 19.3 fJ/conv., demonstrating state-of-the-art energy efficiency.

This brief presents an amplifierless current-to-digital converter (CDC) that uniquely integrates an open-loop pseudo-differential current mirror with a current-integration successive-approximation-register analog-to-digital converter (ADC). The proposed architecture enables the CDC to achieve high-speed operation at low power consumption, which is critical for the intended applications in dynamic optical coherence tomography (OCT) systems. Fabricated in 65-nm CMOS, the prototype occupies 0.019 mm2, consumes$380~\mu $W from a 1-V supply, and achieves a 47-dB dynamic range (DR) with a 50-MS/s sample rate. It achieves Walden’s and Schreier’s figures of merit of 92 fJ/step and 148 dB, respectively, both being the best among reported CDCs.

This work presents a low-power, large cross-scale dynamic range (DR) successive approximation register (SAR) based light-to-digital converter (LDC) designed for wearable multi-wavelength photoplethysmogram (MWPPG) readout. The proposed SAR-LDC employs a current-integration SAR (CI-SAR) quantizer that directly integrates the photocurrent onto a binary capacitive digital-to-analog converter (DAC) and utilizes low-power SAR logic for direct digitization. This approach releases the various trade-offs present in the recent LDC designs and further maximizes the LDC’s power efficiency. At the circuit level, an AC/DC correlated DR enhancement loop, controlled by a digital reconfigurable unit (DRU), enhances both the DC and AC DR of the proposed system. The proposed architecture is fabricated in standard 180-nm CMOS technology. By utilizing a 10-bit SAR-LDC, it achieves a maximum effective number of bits (ENOB) of 9.93 and 12.56 in the Nyquist bandwidth and PPG bandwidth, respectively. The SAR-LDC reads MWPPG on a single channel through time multiplexing, consuming 9.84 μW only while achieving a cross-scale AC DR of 103.4 dB and a total DR of 148.9 dB without using any hybrid circuit technique. The proposed SAR-LDC is further validated using with a commercial PPG sensor for finger MWPPG measurement.

This paper presents a first-order noise shaping (NS) successive approximation register (SAR) analog to digital converter (ADC) utilizing an innovative voltage controlled oscillator (VCO)-based charge-accumulation (CA) integrator. The proposed VCO-CA integrator is highly digital and dynamic, making it energy efficient and compatible with process scaling. Additionally, it can provide a highly linear gain thanks to the small amplitude of residual voltage and the proposed oscillation time control, avoiding the system nonlinearity problem in VCO-based integrators in conventional VCO-based$\mathrm {\Delta \Sigma }$ADCs. Combined with a pulse width (PW)-controlled tunable charge-accumulation circuit, it forms an active loop filter for the first-order NS-SAR ADC, resulting in an innovative fully dynamic VCO-based NS-SAR ADC that achieves a sharp noise transfer function (NTF) without any background gain calibration. The prototype ADC is implemented in a 65-nm GP CMOS process, achieving 77.7 dB SNDR and 79.9 dB DR over a bandwidth of 625 kHz. The total power consumption is$108.3~\mu $W, resulting in a Schreier figure of merit of 175.3 dB.

This article presents a power-efficient high-performance bandpass Delta-Sigma modulator (BPDSM) based on passiveN-path filters (NPF) for direct digitization of intermediate-frequency (IF) signals in wireless receivers. NPF-based BPDSMs have recently been introduced, offering excellent power efficiency and flexible IF frequencies. However, the reported ones recorded a relatively narrow bandwidth, had a redundant passband around DC, and were demonstrated only with a single-bit quantizer. In this work, we report the first NPF-based BPDSM that removes the redundant DC passband using a special NPF for extended bandwidth and improved power and area efficiency. For this reason, it is called a pure BPDSM. Furthermore, we demonstrate that the NPF-based BPDSM works well with a multi-bit quantization approach for improved performance. A fourth-order BPDSM prototype was designed and fabricated in a 65-nm CMOS process, occupying an active area of 0.086 mm2. It features an IF tuning range from 100 to 500 MHz with a signal-to-noise-plus-distortion ratio (SNDR) greater than 60 dB over a fixed 8-MHz bandwidth. Clocked at 700 MHz (IF = 175 MHz), the BPDSM achieves a peak SNDR of 76.7 dB over the 8-MHz bandwidth while dissipating 2.84 mW from a 1.2-V supply, leading to a Schreier’s figure-of-merit of 171.2 dB, the highest among reported BPDSMs of any type.

Wide bandwidth and power-area efficient front-ends are required in emerging implantable biosensor applications, e.g., wireless artificial vision systems for the limited vision. This work presents a low-power 0.031 mm$^{2}~3$-MHz bandwidth noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) tailored for implantable biosensor applications. A highly energy- and area-efficient reset-free residue-processing scheme is proposed. This scheme facilitates noise transfer function (NTF) optimization by enabling control over complex poles. It establishes a unique auxiliary feedback path from the infinite impulse response (IIR) back to the finite impulse response (FIR) by eliminating the need for the FIR filter’s reset phase. This auxiliary feedback loop, which could not be achieved in previous FIR-IIR structures, is a key enabler for achieving high energy efficiency and design flexibility. The in-band quantization noise suppression is boosted by the proposed complex conjugate poles optimization technique, while a low$kT/C$input-referred noise has resulted. The prototype, fabricated in 65-nm CMOS technology with a 7-bit digital-to-analog converter (DAC), consumes$370~\mu $W from a 1-V supply and occupies an active area of only$0.17\times 0.18$mm (0.031-mm2). Operating at an 80-MHz oversampling frequency, the proposed ADC achieves a signal-to-noise and distortion ratio (SNDR) of 70.2 dB over a 3 MHz bandwidth, demonstrating its small area, high efficiency, and high performance for implantable biosensor applications that require high data rates.

This paper presents a low-power high-accuracy key-word spotting (KWS) system based on analog passive switched-capacitor (SC) bandpass filters (BPF). The proposed system inno-vatively extracts the Mel-frequency cepstrum coefficient (MFCC) features with all-analog circuits, providing a better spotting performance than the present analog short-time amplitude or energy features under the same condition. At the circuit level, the analog-MFCC extraction includes the low-noise amplifier, BPF, squarer, integrator, and discrete cosine transformer. And thanks to the effective analog-MFCC features, the size of the fully-connected neural network (FCNN) classifier in our KWS system is enormously reduced. A high-order and fully-differential BPF is also proposed, achieving ultra-low power and high dynamic range by combining zero and pole generation stages rather than building stages separately in traditional ways. Fabricated in 0.18-$\mu \text{m}$CMOS, our filterbank of eight BPFs is measured with a power consumption of 83.2 nW, with a 69.7 dB dynamic range at 5% THD, having advantages over other SC BPFs with similar functions. The total power consumption of our feature extractor is 661.7 nW, achieving an accuracy of 96.6% in two-keyword spotting by an FPGA-based, 15k bit parameter FCNN with a 9.6$\mu \text{s}$latency.

This manuscript presents an ultra-low power acoustic feature extractor for always-on voice activity detection (VAD). It extracts voice features by a 10-band passive switched-capacitor (SC) bandpass filter (BPF) bank and digitizes the features using a passive SC envelope-to-digital converter at the low feature rate. The SC feature extractor minimizes the impact of process-voltage-temperature (PVT) variation at the circuit level, and is thereby free from costly chip-wise training or calibration while at the same time being capable of achieving a classification accuracy matching the state of the arts. Experimental results from a VAD feature extractor prototype fabricated in a 0.18-μm CMOS validate the effectiveness of the proposed techniques. It achieves an averaged 90%/86% speech/non-speech hit rates at 10 dB signal-to-noise ratio for all tested chips based on a universal classifier trained with data from one chip. The feature extractor is mostly passive and thus a low power consumption of 270 nW is achieved. In addition, the proposed feature extractor is frequency-scalable, which allows power-efficient multi-purpose acoustic system implementation.

This article presents a circuit technique to improve the power efficiency of the well-established active-RC continuous-time (CT) Delta-Sigma modulator (DSM). The technique is to add a large capacitor at the virtual ground node of the first amplifier in an active-RC DSM. Without attenuating the in-band signal, this capacitor smooths out the fast transitions in the feedback and suppresses most of the quantization noise before processing by the first amplifier. The transconductance and output swing requirements of the crucial first amplifier can therefore be significantly relaxed. In addition, the technique converts an undesired parasitic pole into a desired one of the loop filter, reducing an amplifier and eliminating the problems associated with the parasitic pole. Last, the large capacitor at the virtual ground node opens a way to reduce the flicker noise because it allows the first amplifier to use large-sized input transistors without performance penalties. To verify the technique, a 3rdorder 1-bit active-RC DSM is designed and fabricated in 180-nm CMOS technology. Clocked at 320 MHz, it achieves a measured signal-to-noise-plus-distortion ratio of 78.7 dB over a 2 MHz bandwidth and a spurious-free dynamic range of 88.4 dB while consuming 0.59 mW, of which the first amplifier takes only 13.5%. The recorded Warden's and Schreier's figure of merits are 20.1 fJ/conv-step and 174 dB respectively. The proposed simple circuit technique makes this otherwise ordinary active-RC modulator one of the most power-efficient CT DSMs.

A highly linear multi-level switched-capacitor (SC) digital-to-analog converter (DAC) is proposed for continuous-time delta-sigma modulators (CTDSMs). A Gm-C CTDSM with a passive frontend low-pass filter (LPF) is further proposed to mitigate the problems of increased settling requirements and worsened anti-aliasing capability (consequences of an SC DAC) so as to realize an extremely power-efficient CTDSM. A 100-kHz bandwidth 40× oversampling 3rd-order CTDSM prototype employing the proposed DAC and modulator topology is fabricated in a low-leakage 65-nm CMOS technology. Experimental results show that the modulator achieves a spurious-free dynamic range (SFDR), dynamic range (DR) and signal-to-noise and distortion ratio (SNDR) of 86.6 dB, 85.1 dB and 78.8 dB, respectively. To the best of our knowledge, this is the first silicon-proven CTDSM with a more-than-3-level DAC that leads to an excellent SFDR while not requiring dynamic element matching, component calibration, precise reference voltages, or an operating frequency higher than the modulator's sampling frequency. The prototype consumes 22.8 μW from a 1.2-V supply, amounting to a Walden's and Schreier's figure of merit (FoM) of 16 fJ/conv.-step and 181.5 dB, respectively, which is the best among state-of-the-art CTDSMs. It further achieves high alias rejections of 52 dB and 58 dB at twice and thrice of the sampling frequency, respectively, and can tolerate a clock period jitter of 3 ns.

Active-RC continuous-time Delta-Sigma modulators (CTDSMs) are an attractive solution for power-efficient and precise analog-to-digital conversion. Multi-bit CTDSMs offer reduced jitter sensitivity and lower over-sampling ratios, which make them suitable for wideband applications compared to their single-bit counterparts. However, they suffer from the problem of element mismatches in their digital-to-analog converters (DACs). On the other hand, in state-of-the-art CTDSMs, the DACs can consume a significant percentage of the overall power. In this manuscript, we present an active-RC CTDSM with a novel 5-level highly linear switched-capacitor (SC) DAC, which reduces power consumption through charge recycling. Splitting a DAC capacitor into two halves helps avoid harmonic distortions caused by signal-dependent timing of DAC pulses. A 10-MHz bandwidth modulator with an 800-MHz sampling frequency (fs) is designed in a 65-nm CMOS technology. Transistor-level simulations show that it achieves 75.9 dB SNDR and 88.8 dB SFDR while consuming 1.28 mW from a 1.2-V supply. Despite the DAC being of the SC type, the modulator achieves high aliasing rejection ratios of 68.8 dB and 65.9 dB at fsand 2fs, respectively.

Recent progress in continuous-time (CT) Delta-Sigma modulators (DSMs) research has shown that applying a passive RC low-pass filter (LPF) in the feedback path can significantly improve the power efficiency of a CT DSM. On the other hand, to achieve high performance, a CT DSM faces the adverse effects of clock jitter, intersymbol interference (ISI), or degradation of antialiasing ability. These challenges are extremely difficult to tackle simultaneously without consuming excessive power. This paper proposes a Gm-C DSM with a combined RC and switched-capacitor LPF frontend stage to achieve a high performance against aliasing, clock jitter, and ISI simultaneously while having an extremely low power consumption. Transistor-level simulations on an audio band modulator and a 10-MHz bandwidth modulator are given, verifying the high immunity of the proposed circuit to clock jitter, ISI, and aliasing while attaining a power efficiency up to 7.4 fJ/conversion step.

This paper presents an on-chip technique for calibrating static and dynamic DAC errors in a multibit continuous-time (CT) Delta-Sigma (ΔΣ) modulator. Dynamic errors such as inter-symbol-interference (ISI) affect the DAC output at every data transition and significantly deteriorate the in-band noise floor in high-speed applications. In the proposed technique, a compensation current is injected in the loop at every up-transition of input data to cancel the ISI error of each unit cell, thus improving its dynamic linearity. High linearity merged-input-feedback Gm-C integrators have been shown to enhance the converter's linearity and reduce power but require that the feedback DAC common mode matches the input-signal common mode. A biasing circuit for the current-steering feedback DAC is proposed to match its output common mode to the input signal common mode across PVT. Simulation results for a 70 MHz bandwidth, 3rdorder modulator, operating at a 2.8 GHz sampling rate, show a 2.8dB improvement in the in-band noise with the proposed dynamic calibration technique as well as maintaining the common-mode matching requirements across PVT.

A power-efficient active-RC continuous-time Delta-Sigma modulator (CT-DSM) circuit topology is proposed with a lowpass filter (LPF) capacitor placed at the virtual ground node of the first integrator. A parasitic capacitor always exists at the virtual ground node of an active-RC integrator, generating an unwanted high-frequency pole. With a deliberately added large capacitor at the virtual ground node, the parasitic pole turns into a wanted low-frequency pole for the loop filter of the CT-DSM. Together with its DC pole, the active-RC integrator now realizes two poles for the CT-DSM, reducing amplifiers needed in the modulator. Furthermore, the built-in LPF significantly attenuates and smoothens out the sharp edges of the current to the integrating capacitor, thereby greatly reduces the slew-rate and bandwidth requirements of the crucial first amplifier in the modulator for lower power consumption. A design example for Bluetooth applications is implemented in a 0.18-μm CMOS technology. Simulations show that it achieves 79dB SNDR over 2 MHz bandwidth with 393μW power consumption from 1.8V, which corresponds to a FOM of 13.6 fJ/conv.-step.

This paper proposes a new most significant bit (MSB)-prediction switching scheme and presents an energy-efficient successive approximation register (SAR) analog-to-digital converter (ADC) using the proposed scheme. The prediction of the MSB is conducted before the sampling phase, and the MSB-1 conversion switches all the capacitors of the capacitive digital-to-analog converter (CDAC) from the references set by the prediction result after the sampling phase. Therefore, the reference voltage in the proposed scheme is reduced by half to satisfy the same input range. Compared with the regular Vcm-based CDAC, the proposed technique exhibits a 75.1% reduction in switching energy and a reduction ratio of (1/2)1/2in nonlinearity under the same capacitor area and matching condition. A 10-bit SAR ADC prototype is designed and simulated in a 180-nm CMOS process to validate the proposed technique. The ADC consumes $31.16~\mu \text{W}$ from a 1-V supply and the input range of [-2 V, 2 V]. The simulated signal-to-noise-and-distortion ratio is 61.01 dB at 2 MS/s, benefited from the redundant capacitors added to the CDAC.

A technique to ease the linearity requirement of the input transconductor (Gm) of a Gm-C based continuous-time (CT) Delta-Sigma (ΔΣ) modulator is presented. Compared with RC-based CT ΔΣ modulators, Gm-C-based modulators consume lower power, however they have poorer SNDR due to smaller linear input range. The proposed technique utilizes a single bit quantiser, a 14-tap FIR filter and a compensating Gm cell in the feedback path to cancel the input Gm cell's nonlinearity. System level simulations of a 3rd order modulator demonstrate an improvement of over 30 dB in SFDR with no penalty on the in-band noise floor.

This paper presents a successive-approximation-register (SAR) analogue-to-digital converter (ADC) using a tri-level switching scheme named as reverse VCM-based scheme which maintains good linearity without any driving and accuracy requirements on VCM. A 10-bit SAR ADC is designed in a 0.18 CMOS technology. With a unit capacitor size of 17.2 fF, the ADC consumes 41.9 μW from a 1.8 V voltage supply. The measured signal-to-noise-plus-distortion ratio (SNDR) is 59.6 dB at 2 MS/s. The figure-of-merit (FOM) is 26.9 fJ/conv.-step.

This paper presents a novel low-voltage CMOS smart temperature sensor targeted for VLSI thermal management. A polyresistor is used as the sensing element and digitization is performed in the time domain. The proposed temperature-sensing concept can be realized with simple circuits that operate at low supply voltages, which are compatible with the digital circuits in VLSI systems. Fabricated in 90-nm CMOS, the sensor can operate with a supply voltage as low as 0.8 V and features a supply sensitivity of 4°C/V. After 50-sample moving-average and a two-point calibration at 25°C and 45°C, the design achieves an inaccuracy of -0.6°C/0.8°C over -40°C-125°C. It dissipates only 11.8 uW at a sampling rate of 5 kS/s from a 0.9-V nominal supply.

This paper presents a low power, long-transmission distance, high data rate intrabody communication (IBC) analog receiver front end (RFE). First, to optimize the transmission performance, conventional transmission line analysis scheme is creatively adopted to the IBC design to characterize the body channel. Second, switched-capacitor filters based on sampling rate boosting technique are adopted for higher accuracy and lower power consumption. Third, a novel RFE topology is proposed to further enhance the IBC performance. The new RFE is designed and fabricated in a standard 180-nm CMOS process. Measurement results show that the RFE can successfully transmit data spanning the whole human body, around 180 cm, which is one of the longest transmission distances reported in related literatures. Furthermore, it reaches a maximum data rate of 2.5 Mb/s with a bit error rate less than 1e-7 and consumes 5.4 mW from a 1.8 V supply. The proposed RFE compares favorably to similar reported works.

As fabrication process technology continues to advance, mask set costs have become prohibitively expensive. Structured application specific integrated circuits (sASICs) offer a middle ground in price and performance between ASICs and field-programmable gate arrays (FPGAs) by sharing masks across different designs. In this paper, two sASIC architectures are proposed, the first being based on three-input lookup-tables, and the second on AOI22 gates. The sASICs are programmed using a standard-cell compatible design flow. They are customized using a minimum of three masks, i.e., two metals and one via. The area and delay of the sASIC are compared with ASICs and FPGAs. Results over a set of benchmark circuits show that our AOI22-based sASIC had an average of 1.76x/1.41x increase in area/delay compared to ASICs, a considerable improvement compared with the 26.56x/5.09x increase for FPGAs. This is, to the best of our knowledge, the best performance reported in the literature for a practical sASIC. A prototype using the sASIC was fabricated using a universal machine control 0.13-μm mixed-mode/RF process. It was fully verified using scan and functional tests, and used in a demonstration system.

This paper presents the analysis of a calibration technique for high-resolution successive-approximation register analog-to-digital converter (SAR ADC) using a calibration digital-to-analog converter (DAC), which simplifies the complicated relationships among various design parameters and provides design insight that aids in parameter selection. Based on this analysis, an energy-efficient, 14-bit resolution SAR ADC is realized in a 0.18µm CMOS technology. The relationships among the following factors are analyzed in details: (1) the main DAC resolution, (2) the calibration accuracy, (3) the capacitor value to be calibrated, and (4) the parasitic capacitors. Post-layout simulation results are presented and specifically Monte Carlo (MC) shows promising result that is in agreement with the proposed calibration technique.

In this paper, a new overshoot cancellation method is presented for comparator-based pipelined ADCs. By introducing charging and discharging operations in two adjacent stages, the large overshoot in each stage can be either tolerated as sub-ADC error or cancelled out with each other. Applying this concept, a 10-bit pipelined ADC has been designed and simulated in a 0.18-μm CMOS process. It achieves 57.2dB SNDR at 20MS/s and consumes 2.6mW under 1.8 V supply, resulting in an ENOB of 9.2-bit and an FOM of 0.221 pJ/Conv.-step.

We describe the architecture of a structured ASIC fabric in which the logic and routing can be customized using three masks. A standard Cadence based design flow is employed, and using an active dynamic backlight controller as an example, performance is compared to that of an ASIC implementation in the same technology.

A Structured Application-specific Integrated Circuit (SASIC) is a programmable fabric in which a small set of masks are customized for a particular application, serving to reduce the associated non-recurring engineering cost (NRE). In this paper we describe the implementation of a SASIC logic cell which is programmable via a single metal layer. A SASIC fabric prototype is fabricated and all implemented functions are verified on silicon. Experimental measurement verifies correct operation of our SASIC with a clock frequency of over 250 MHz.

As fabrication process technology continues to advance, mask set costs have become prohibitively expensive. Structured ASICs can offer price and performance between ASICs and FPGAs. They are attractive for mid-volume production and offer good intellectual property security. In this paper, a structured ASIC methodology, where 2 metal- and 1 via-mask are customised, is described. The CAD tools are fully compatible with conventional ASIC design flows and a comparison of area and delay performance with ASICs and FPGAs is given. A prototype structured ASIC implementing an LED-backlit LCD controller was fabricated in a 0.13 μm CMOS process. It was verified and power consumption compared with an ASIC design.

In this paper, we will present an effective layout method for analog circuits. We consider symmetry constraint, common centroid constraint, device merging and device clustering during the placement step. Symmetric routing will then be performed. In order to have successful routing, we will perform analog-based routability-driven adjustment during the placement process, taking into account for analog circuits that wires are not preferred to be layout on top of active devices. All these concepts were put together in our tool. Experimental results show that we can generate quality analog layout within minutes of time that passes the design rule check, layout-schematic verification and the simulation results are comparable with those of manual design, while a manual design will take a designer a couple of days to generate.

Via-programmable gate arrays (VPGAs) offer a middle ground between application specific integrated circuits and field programmable gate arrays in terms of flexibility, manufactuing cost, speed, power and area. In this paper, we present a novel VPGA logic cell, the complementary universal logic gate (CULG) which can be used to implement both sequential and combinatorial elements. Its performance is compared with a number of other designs including transmission gate, differential cascode voltage switch with pass gate, and standard cell. The CULG is found to have comparable power-delay product and process variation sensitivity to the other designs while offering the lowest power consumption.

In this paper, a low-power signal processing front-end and PIE decoder for use in UHF RFID passive transponders is presented. By merging with the decoder, the clock generator does not need to drive a large loading capacitor. Therefore, its power consumption can be greatly reduced. In addition, the ring oscillator of the generator was designed for low sensitivity to supply voltage variation and low power consumption. Fabricated in a 0.13-mum CMOS process, the measured power consumption consumes only 850 nW.

This paper investigates and resolves in-channel/quadrature channel (I/Q) imbalances in quadrature band pass delta sigma modulators. These mismatches result in image interference and noise being aliased into the desired signal band, thus degrading the dynamic range of the modulators. A novel dynamic element match shaping scheme is proposed to cancel the aliasing of image interference, noise, and self-image. The simulation results for the proposed scheme show that the SNDR is only degraded by 1.6 dB from the ideal case (without I/Q mismatch). Meanwhile, using the I/Q channel multiplexing technique, operational amplifiers, quantizers, and digital-analog converters can be shared between I/Q channels. As a result, silicon area can be reduced with the same power consumption.

In order to reduce parasitic mismatch in analog circuits, some groups of devices are required to share a common centroid while being placed. Devices are split into smaller ones and placed with a common center point. We will address this problem of handling common centroid constraint in placement. A new representation called Center- based Corner Block List (C-CBL) is proposed which is a natural extension of Corner Block List (CBL) [1] to represent a common centroid placement of a set of device pairs. C-CBL is complete and non-redundant in representing any common centroid mosaic packings with pairs of blocks to be matched. To address the same problem with an additional constraint that devices are required to be placed uniformly to average out the parasitic errors, a grid-based approach is proposed. Experimental results show that both approaches are fast and promising, and have high scalability that even large data sets can be handled effectively.

A new dynamic element matching (DEM) technique is proposed to reduce the combined problem of non-linearity within the multi-bit digital-to-analog converters (DAC) and I/Q mismatches in the feedback paths of quadrature delta-sigma (ΔΣ) modulators. Under this scheme, the non-linearity effect of I and Q DACs is suppressed by data-weighted averaging (DWA) individually. At the same time, the two DACs are swapped according to the element selection pointers of DWA. Consequently, the image is restrained by this time-interleaved swapping. The overhead of this scheme is minimal. Extensive MATLAB simulations were performed to evaluate the performance of this scheme. With a 3rd order, 64 oversampling ratio quadrature delta-sigma modulator, this scheme shows 10dB and 25dB improvement in signal-to-noise-plus-distortion ratio (SNDR) and image rejection ratio (IRR) respectively for the case of 2-bit ΔΣ modulator.

This paper presents a current-mode analog-to-quaternary (A/Q) converter using a 0.35/spl mu/m CMOS process. Redundant signed digit (RSD) technique is used to improve the resolution to 6 digits, which is equivalent to 12 binary bits. Simulations results show that the converter dissipates 382mW at 2.5V supply and 20MHz sampling rate. The converter achieves SNDR of 66.8dB, SFDR of 76.33dB and THD of -75.73dB. The effective number of bit is equal to 5.4 digits or 10.8 bits (binary).

This paper introduces a new algorithm of extracting MFCC for speech recognition. The new algorithm reduces the computation power by 53% compared to the conventional algorithm. Simulation results indicate the new algorithm has a recognition accuracy of 92.93%. There is only a 1.5% reduction in recognition accuracy compared to the conventional MFCC extraction algorithm, which has an accuracy of 94.43%. However, the number of logic gates required to implement the new algorithm is about half of the MFCC algorithm, which makes the new algorithm very efficient for hardware implementation.

This paper presents a fully differential OTA with a supply of 0.5V in a 0.18/spl mu/m CMOS process that has threshold voltages of 0.5V under zero body-source biasing. Unlike a recent two-stage 0.5V OTA architecture, this OTA employs two common mode feedback loops for obtaining a stable operating condition and thus a robust performance against process variations. Body terminals of the input differential pairs of each stage are used for common mode control. Simulation results indicate that this OTA has an open-loop gain of greater than 61dB, a unity gain-bandwidth of 41MHz with a load of 10pF. The power consumption is 510/spl mu/W.

In this paper a 173-bit type II ONB ECC processor for inductive RFID applications is described. Compared with the standard mathematical expressions provided by A. J. Menezes (1993), the formula expressions adopted in the design can save one field multiplication operation in the curve addition. Therefore, the encryption/decryption time is reduced by approximately 7%. Furthermore, the system level architecture of the ECC processor is specially structured and optimized, which makes it faster and less power consuming, and is more favorable for inductive RFID systems.

In this paper, a CMOS low noise amplifier (LNA) employing the switched-capacitors is proposed to perform multi-band tuning for an MB-OFDM ultra-wideband (UWB) hopping system. By using the fully differential topology, the switching noise generated during each frequency transition interval is greatly suppressed. The proposed UWB LNA is implemented in a standard 0.18-/spl mu/m CMOS process. The simulation results show that it is capable of performing the fast switching with a settling time of less than 3 ns. Furthermore, the switching noise voltage at the output is rapidly reduced to less than 1 /spl mu/V within 5 ns. The designed circuit is optimized in each center frequency, achieving the maximum power gain of 16.2 dB and the minimum noise figure of 2.63 dB.

In this paper, an electrocardiographic (ECG) signal processing IC, which is used for portable biomedical application, was designed using continuous-time technique. The circuit consists of an instrumentation amplifier (INA) with driven-right-leg circuit (DRL), a 5th order G/sub m/-C low pass filter (G/sub m/-C LPF) operating in sub-threshold mode, and amplifiers. DRL circuit is used to detect small amplitude signal in the presence of large common-mode voltage from the human body. The CMRR of the INA is 78 dB and the G/sub m/-C LPF has a cutoff frequency of 18 Hz. As a result of using the DRL, a small signal can be detected in the presence of large common-mode differential. The circuit consumes 1.23 mW when operating from with a supply voltage of /spl plusmn/1.5-V and occupies a core area of 0.94 mm/sup 2/. The circuit was designed in a 0.35/spl mu/m CMOS process and simulation results have successfully demonstrated the functionalities.

In this paper, we propose a power-efficient bitstream parsing for H.264/AVC baseline profile decoding. It parses the input bitstream syntaxes and controls the following decoding steps. Various power reduction techniques, such as data-driven based on statistic results, nonuniform partition, precomputation, guarded evaluation, hierarchical FSM decomposition, clock gating etc., have been adopted in our design. The VLSI implementation results show that under UMC130nm technology with 1.08V supply voltage, the core power consumption is only 1.98mW@20MHz for real-time decoding. Total hardware costs are 49k gates and 1.2 /spl times/ 1.2mm/sup 2/ chip area. The power-efficient and real-time features make our design ideal for low-power video transmission applications such as mobile phone and PDA where video quality is often traded off for energy.

This work examines the inherent self-checking (SC) property of latch-free dynamic asynchronous datapath (LFDAD) using differential cascode voltage switch logic. Consequently, a highly efficient SC dynamic asynchronous datapath architecture is presented. In this architecture, no hardware needs to be added to the datapath to achieve SC. The presented implementation is efficient in terms of speed and area and represents a new approach to fault-tolerant design.

This paper presents a reconfigurable sigma-delta audio Digital-to-Analog Converter (DAC) which is suitable for embedded FPGA applications. The Sigma-Delta Modulator (SDM) design can be configured as a 3rd or 5th order SDM and allows different input word lengths. Different input sampling rates are also entertained by employing a programmable interpolator. The DAC accepts 16-/18-/20-/24-bit PCM data at sampling rates of 32/44.1/48/88.2/96 kHz for applications in CD, SACD and DVD audio.

This work examines the inherent self-checking property of a latch-free dynamic asynchronous datapath (LFDAD) using differential cascode voltage switch logic (DCVSL). Consequently, a highly efficient self-checking (SC) dynamic asynchronous datapath architecture is presented. In this architecture, no hardware needs to be added to the datapath to achieve self-checking. The presented implementation is efficient in terms of speed and area and represents a new approach to fault-tolerant design.

This paper investigates the inherent totally self-checking (TSC) property of one type of dynamic asynchronous datapath based on Differential Cascode Voltage Logic (DCVSL). As a result, a totally self-checking dynamic asynchronous datapath architecture is proposed. It is simpler than other similar approaches and represents a new approach to fault tolerant design.

I/Q mismatches are common in radio receivers, which apply quadrature demodulation schemes. Numerous methods have been developed to estimate and correct these errors for narrow-band signals. In this paper a wideband correction method is introduced. First the frequency-dependent I/Q mismatches are estimated by local test signal injection. Then a digital filter is constructed to correct them. With this method, a significant amount of image rejection over a broad bandwidth can be achieved as demonstrated by high-level simulations.