The growing speed gap between transistors and wire interconnects is forcing the development of distributed, or clustered, architectures. These designs partition the chip into small regions with fast intracluster communication. Longer latency is required to communicate between clusters. The hardware and/or software are responsible for scheduling instructions to clusters such that critical path communication occurs within a cluster. This paper presents GENEric SYstems Simulator (GENESYS), a technology modeling tool that captures a broad range of materials, device, circuit, and interconnect parameters across current and future semiconductor technology. This tool is used to explore the relationship between key technology parameters (intercluster wire delay and transistor switching delay) and key architecture parameters (superscalar versus multithreaded instruction dispatch, and value prediction support). GENESYS is used to predict intercluster latencies as VLSI technology advances. The study provides quantitative data showing how conventional superscalar performance is degraded with increasing wire latency. Threaded designs are more tolerant to wire delay. Optimal thread size changes with advancing VLSI technology, suggesting a highly adaptive architecture. Value prediction is shown to be useful in all cases, but provides more benefit to the multithreaded design.

Single-chip multiprocessors are an important research direction for future microprocessors. The stigma of this approach is that many important applications cannot be automatically parallelized. This paper presents a single-chip multiprocessor that engages aggressive speculation techniques to enable dynamic parallelization of irregular, sequential binaries. Thread speculation and data value prediction are combined to enable the processor to execute dependent threads in parallel. The architecture performs a novel form of dynamic thread partitioning and includes an aggressive correlated value predictor. Microarchitectural structures manage interthread data and control dependencies. On an eight processor system, simulated execution of SPECint95 binaries delivers a speedup of 3.4 over a scalar in-order uniprocessor. This improvement is due entirely to the exploitation of dynamically extracted thread level parallelism.

An important research direction for future microprocessors is the single-chip multiprocessor. The drawbacks of this approach are that many important applications cannot be automatically parallelized and that performance suffers with "dusty-deck" binaries. This paper details a single-chip multiprocessor that engages a combination of aggressive speculation techniques to enable the dynamic parallelization of irregular, sequential binaries. Thread speculation (multiscalar execution) and data value prediction are combined to enable the processor to execute dependent threads in parallel. The architecture performs a novel form of dynamic thread partitioning called MEM-slicing, and includes an extremely aggressive correlated value predictor. Several new microarchitectural structures to manage inter-thread dependencies are described. Simulations show that sequential programs are amenable to this form of execution. Over SPECint95, an average speedup of 3.4 is achieved on 8 processors due entirely to the exploitation of thread level parallelism.

Thread level speculative execution, together with value prediction to break data dependencies between threads, may enable efficient single program execution on a closely coupled chip multiprocessor. This paper describes a method to partition sequential programs such that a minimum number of hard-to-predict data dependencies cross thread boundaries. SPEC95 binaries are partitioned and then executed on an idealized simulator in order to study the limits of this technique. Value prediction is shown to be crucial to exposing thread level parallelism (TLP). Simple value predictors promise modest to large gains if thread boundaries are properly identified. Concurrent execution of fully data independent threads on 8 processors gives a geometric mean speedup of 2.4 for the benchmarks studied.