Demo Data from VLDB 2026 / reviewers in the wild / expert
Chen-Chau Yang
dblp:05/3000
· DBLP profile ↗
5ranked-venue papers
1as first author
0since 2021 · last 2004
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3 · 1 first-authorSoftware engineering, systems software and programming languages · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
4 papers |
Distributed systems · 67% Emerging computing paradigms · 17% Parallel and multicore computing · 8% | |
| Artificial intelligence
2 papers |
Image recognition and object detection · 67% Representation and self-supervised learning · 33% | |
| Software engineering, system software, and programming languages
1 paper |
Requirements engineering and software design · 100% |
Topics — the 6 heaviest of 9, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Requirements engineering and software design
distributed system design |
0.0 | 1 | 1981 | An Approach to Distributed Computing System Software Design · IEEE Trans. Software Eng. 1981 |
Emerging computing paradigms › neuromorphic computing
associative memory |
0.0 | 2 | 1966 | A Cutpoint Cellular Associative Memory · IEEE Trans. Electron. Comput. 1966 Pattern Recognition by Using an Associative Memory · IEEE Trans. Electron. Comput. 1966 |
Computer vision › Image recognition and object detection › character recognition
handwritten character recognition |
0.0 | 1 | 1966 | Pattern Recognition by Using an Associative Memory · IEEE Trans. Electron. Comput. 1966 |
Computer vision › Image recognition and object detection
template matching |
0.0 | 1 | 1966 | Pattern Recognition by Using an Associative Memory · IEEE Trans. Electron. Comput. 1966 |
Parallel and multicore computing › parallel architecture
associative processor |
0.0 | 1 | 1966 | A Nonbulk Addition Technique for Associative Processors · IEEE Trans. Electron. Comput. 1966 |
Integrated circuit design › VLSI design
cellular array |
0.0 | 1 | 1966 | A Cutpoint Cellular Associative Memory · IEEE Trans. Electron. Comput. 1966 |
Methods — techniques the papers use, named apart from their topics
template matching · 0.0sorting scheme · 0.0nonbulk addition · 0.0cellular array design · 0.0associative memory · 0.0adaptive hyperplane adjustment · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2004 | A New Normal Walk Model for Mesh PCS NetworksabstractMovement patterns play a crucial role in evaluating the performance of mobility-dependent personal communication service (PCS) strategies, such as location updating and paging schemes. This study proposes a novel normal walk model to represent more closely the daily mobility patterns of a mobile station (MS) in mesh PCS networks than a conventional random walk model. The proposed model applies an equivalent drift angle 8 to determine the direction in which an MS leaves a mesh cell in the next one step. The angle 8 is assumed to approach a normal distribution with parameters: /spl mu/ = 0/spl deg/ and /spl sigma/ is on the interval [5/spl deg/, 90/spl deg/], based on the concept that most trips follow the shortest path. This assumption implies that varying can redistribute the probabilities associated with 8 to make the normal movement patterns more realistic than the random ones. Moreover, for a = 79.5/spl deg/, a normal walk can behave almost like a conventional random walk. Chiu-Ching Tuan, Chen-Chau Yang |
AINA (1) | 2 |
| 1981 | An Approach to Distributed Computing System Software DesignabstractDistributed computing systems represent a wide variety of computer systems, ranging from a centralized star network to a completely decentralized computer system. The design of software for distributed computing systems is more complicated due to many design constraints and interactions of software components of the system. Stephen S. Yau, Chen-Chau Yang, Sol M. Shatz |
IEEE Trans. Software Eng. | 2 |
| 1966 | A Nonbulk Addition Technique for Associative ProcessorsabstractA process is described for continuing adaptation, after hyperplanes that separate pattern classes in pattern space have been found, in order to increase the distance between sample patterns and hyperplanes. Stephen Sik-Sang, Chen-Chau Yang |
IEEE Trans. Electron. Comput. | 2 |
| 1966 | Pattern Recognition by Using an Associative MemoryabstractThe purpose of this paper is to present a simple template-matching pattern recognition technique by using any general-purpose associative memory. The input patterns for recognition may have wide variations, provided that the distinct features of individual pattern classes can be extracted. Each pattern class is allowed to have deviations in size, style, orientation, etc. within certain limits. This pattern recognition technique is extremely efficient in handwritten character recognition, which is used for illustration in this paper. Because each input pattern is processed with all the pattern classes simultaneously, the speed of this pattern recognition technique is very high. It is found that most input patterns are recognized within first comparison process and no input patterns require more than two comparison processes for their recognition. Stephen Sik-Sang, Chen-Chau Yang |
IEEE Trans. Electron. Comput. | 2 |
| 1966 | A Cutpoint Cellular Associative MemoryabstractDue to the rapidly growing technological ability to batch fabricate a large number of components on one substrate, it is economical and reliable to implement an associative memory by cellular arrays. Such an associative memory is presented in this paper. The proposed memory is word-organized, and its basic building blocks are cutpoint cells with various indices. All the bit-memories, word-sequential-control networks, word-match tag-networks, and bit-output networks have identical structures, and the proposed memory system is especially compatible with the manufacture of integrated circuit. The memory can perform the comparison, tag, writing and nondestructive reading processes in the parallel-by-bit form, as well as Lewin's sorting scheme for ordered retrieval. The dematching process is completely automatic. The memory sequential-control ontrol system does not use any ladder structure which is commonly employed in previous associative memory systems; hence the operation speed is largely increased. The stage delays for various operations are given, and may be employed to estimate the speed of the associative memory. Chen-Chau Yang, Stephen S. Yau |
IEEE Trans. Electron. Comput. | 1 |