Article Free Access Share on The sea-of-wires array synthesis system Authors: Ing-Yi Chen View Profile , Geng-Lin Chen View Profile , Fredrick J. Hill View Profile , Sy-Yen Kuo View Profile Authors Info & Claims DAC '93: Proceedings of the 30th international Design Automation ConferenceJuly 1993 Pages 188–193https://doi.org/10.1145/157485.164664Published:01 July 1993Publication History 2citation442DownloadsMetricsTotal Citations2Total Downloads442Last 12 Months13Last 6 weeks2 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

Digital hardware synthesis implies the use of clock mode register transfer level descriptions. A major feature of this approach to synthesis is the possibility of integrating test generation into the design and synthesis process. Preliminary synthesis makes it possible to link test search at the function level to fault enumeration at the network level. A recently developed backward state justification search has eliminated the final bottleneck in automatic test generation.>

A novel technique for synchronous fault simulation of sequential circuits utilizing surrogate fault propagation and backward fault collection is introduced, and its implementation is evaluated. Fault effects which reconverge over time are simulated as exceptions. Evidence which shows SFSSE (synchronous fault simulation by surrogate with exceptions) to be superior to existing approaches is presented. As in deductive and concurrent simulation, execution time drops dramatically as the majority of faults are detected. SFSSE incorporates features of both deductive and parallel fault simulations while avoiding the drawbacks of each of these techniques. In contrast to deductive simulation, fault lists are processed only at primary outputs and memory elements. This is critical with respect to both execution time and storage requirements.>

This paper treats the automatic translation of register transfer level (RTL) descriptions of digital systems to VLSI realization. The target technology is the storage logic array or SLA. The approach is aimed at applications where the emphasis is on reducing engineering effort and design turnaround time rather than maximizing chip area utilization. The paper develops a mapping between the register transfer language, AHPL, and the SLA. It is shown that each primitive explicitly appearing in an AHPL description can be mapped into an area of real estate in an SLA realization. A detailed development of some of the algorithms is presented. The entire process has been successfully implemented and applied to a set of examples. This is accomplished by developing a final stage for an already existing three-stage multi-application compiler for AHPL. Layout and routing are shown to be a single optimization process if the hardware target is an SLA.

Describes the extension and formalization of the hardware description language AHPI to form AHPL III. This language provides for nesting AHPL descriptions within descriptions. It incorporates a general index extension mechanism which permits the efficient representation of sets of duplicate descriptions of any complexity. Three types of structures, procedural structures, functional registers, and combinational logic units are permitted. Procedural structures may be primitive or nonprimitive. All but primitive procedural structures share a common syntax. Nesting, declaration, and invocation rules for these distinct structures are specified in a semantics table.

This paper describes SCIRTSS (a sequential circuit test search system). An analytical basis is given for using tree search techniques in determining test sequences for sequential circuits. The basic algorithm for the system of SCIRTSS programs is described and the extent to which the user can influence the search procedure is discussed. Included are the results of the application of SCIRTSS to eight sequential circuits of varying complexity on each one of which it succeeded in finding a fault detection sequence for at least 98 percent of the simple logical faults. This suggests that SCIRTSS can be effective on more complex LSI parts than other automatic test generation methods currently available. Breaking the tree search into two separate search procedures and partitioning circuits when possible into control and data sections are unique features which contribute to SCIRTSS efficiency.