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Thor Bestul

dblp:05/4048 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 1989
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Artificial intelligence and machine learning · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Parallel and multicore computing · 75% Processor architecture and microarchitecture · 25%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Parallel and multicore computing
histogram computation
0.011989
On Computing Complete Histograms of Images in Log (n) Steps Using Hypercubes · IEEE Trans. Pattern Anal. Mach. Intell. 1989
Parallel and multicore computing › multiprocessor system › distributed-memory multiprocessor
hypercube multiprocessor
0.011989
On Computing Complete Histograms of Images in Log (n) Steps Using Hypercubes · IEEE Trans. Pattern Anal. Mach. Intell. 1989
Parallel and multicore computing
parallel algorithms
0.011989
On Computing Complete Histograms of Images in Log (n) Steps Using Hypercubes · IEEE Trans. Pattern Anal. Mach. Intell. 1989
Processor architecture and microarchitecture
SIMD
0.011989
On Computing Complete Histograms of Images in Log (n) Steps Using Hypercubes · IEEE Trans. Pattern Anal. Mach. Intell. 1989

Methods — techniques the papers use, named apart from their topics

suffix-based addressing · 0.0SIMD hypercube · 0.0
YearPublicationVenuePosition
1989 On Computing Complete Histograms of Images in Log (n) Steps Using Hypercubes
abstract
An algorithm for the computation of the histogram of limited-width (such as gray-level) values on a SIMD (single-instructions multiple-data) hypercube multiprocessor is proposed, which does not require the use of a general interconnection capability such as that on the connection machine. The computation of the complete histogram of n such values takes place in a series of log n steps, after which the histogram for value i can be found in the lowest-addressed processor whose address ends in i. The algorithm makes use of the association of suffixes of data values of increasing width with suffixes of processor addresses.>
Thor Bestul, Larry Davis 0001
IEEE Trans. Pattern Anal. Mach. Intell.1