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Hideya Horikawa

dblp:05/4324 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 1987
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 100%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › physical design › placement
gate assignment		 0.011987
A Heuristic Algorithm for Gate Assignment in One-Dimensional Array Approach · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1987
Electronic design automation
physical design		 0.011987
A Heuristic Algorithm for Gate Assignment in One-Dimensional Array Approach · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1987
Electronic design automation › physical design
placement		 0.011987
A Heuristic Algorithm for Gate Assignment in One-Dimensional Array Approach · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1987

Methods — techniques the papers use, named apart from their topics

heuristic algorithm · 0.0
YearPublicationVenuePosition
1987 A Heuristic Algorithm for Gate Assignment in One-Dimensional Array Approach
abstract
In this paper, we present a new approach for the one-dimensional gate assignment problem. The original minimization problem is transformed into a restricted problem, and then a new heuristic algorithm is applied to it. The solution obtained by the algorithm is interpreted as a solution for the original problem. The whole process of the approach has been implemented and tested with various examples. Experimental results show that our approach can approximately produce optimum solutions.
Takashi Fujii, Hideya Horikawa, Tohru Kikuno, Noriyoshi Yoshida
 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.2