Body awareness is relevant for the efficacy of psychotherapy. However, previous work on virtual reality (VR) and avatar-assisted therapy has often overlooked it. We investigated the effect of avatar individualization on body awareness in the context of VR-specific user experience, including sense of embodiment (SoE), plausibility, and sense of presence (SoP). In a between-subject design, 86 participants embodied three avatar types and engaged in VR movement exercises. The avatars were (1) generic and gender-matched, (2) customized from a set of pre-existing options, or (3) personalized photorealistic scans. Compared to the other conditions, participants with personalized avatars reported increased SoE, yet higher eeriness and reduced body awareness. Further, SoE and SoP positively correlated with body awareness across conditions. Our results indicate that VR user experience and body awareness do not always dovetail and do not necessarily predict each other. Future research should work towards a balance between body awareness and SoE.

Abstract. If [Formula: see text] is a lattice polytope (i.e., [Formula: see text] is the convex hull of finitely many integer points in [Formula: see text]) of dimension [Formula: see text], Ehrhart’s famous theorem [ C. R. Acad. Sci. Paris, 254 (1962), pp. 616–618] asserts that the integer-point counting function [Formula: see text] is a degree-[Formula: see text] polynomial in the integer variable [Formula: see text]. Equivalently, the generating function [Formula: see text] is a rational function of the form [Formula: see text]; we call [Formula: see text] the [Formula: see text] -polynomial of [Formula: see text]. There are several known necessary conditions for [Formula: see text]-polynomials, including results by Hibi [ Discrete Math., 83 (1990), pp. 119–121], Stanley [ J. Pure Appl. Algebra, 73 (1991), pp. 307–314], and Stapledon [ Trans. Amer. Math. Soc., 361 (2009), pp. 5615–5626], who used an interplay of arithmetic (integer-point structure) and topological (local [Formula: see text]-vectors of triangulations) data of a given polytope. We introduce an alternative ansatz to understand Ehrhart theory through the [Formula: see text]-polynomial of the boundary of a polytope, recovering all of the above results and their extensions for rational polytopes in a unifying manner. We include applications for (rational) Gorenstein polytopes and rational Ehrhart dilations.

We investigate the arithmetic-geometric structure of the lecture hall cone $L_n \ := \ \big\{\lambda\in \mathbb{R}^n: \, 0\leq \frac{\lambda_1}{1}\leq \frac{\lambda_2}{2}\leq \frac{\lambda_3}{3}\leq \cdots \leq \frac{\lambda_n}{n}\big\}$. We show that $L_n$ is isomorphic to the cone over the lattice pyramid of a reflexive simplex whose Ehrhart $h^*$-polynomial is given by the $(n-1)$st Eulerian polynomial and prove that lecture hall cones admit regular, flag, unimodular triangulations. After explicitly describing the Hilbert basis for $L_n$, we conclude with observations and a conjecture regarding the structure of unimodular triangulations of $L_n$, including connections between enumerative and algebraic properties of $L_n$ and cones over unit cubes.

High quality is an absolute necessity for automotive designs. This paper describes an approach to improve the overall defect coverage for CMOS-based high quality automotive designs. We present results from a cell-aware (CA) characterization flow for 216 cells, the pattern generation flow for a 130nm smart power design, and high-volume production test results achieved after testing multimillion parts. The idea behind CA tests is to detect cell-internal (CI) bridges, opens, leaking and high resistive transistor defects which are undetected with state-of-the-art tests. The production test results have shown that the CA tests detect various failing parts during a first wafer sort test which still resulted into unique failing parts after a second wafer sort test done at a different temperature and with additional tests. The obtained results encouraged us to continue this work beyond this paper to run further experiments with the final goal to eliminate the stuck-at (SA) and transition delay (TR) test by simultaneously improving the quality with CA tests which are a superset of SA and TR tests.

The convex hull of the roots of a classical root lattice is called a root polytope. We determine explicit unimodular triangulations of the boundaries of the root polytopes associated to the root lattices $A_n$, $C_n$, and $D_n$, and we compute their f- and h-vectors. This leads us to recover formulae for the growth series of these root lattices, which were first conjectured by Conway, Mallows, and Sloane and Baake and Grimm and were proved by Conway and Sloane and Bacher, de la Harpe, and Venkov. We also prove the formula for the growth series of the root lattice $B_n$, which requires a modification of our technique.

This paper reports the experience being made during the implementation of low pin count techniques and their insertion into a production environment. The techniques applied are "on-loadboard compare" and "shared driver". Already known on a concept level for an on-chip approach, in this paper the transfer to an on-loadboard solution is presented. Emphasis is put on production related aspects. Practical experience, challenges, and pitfalls are described to allow a better assessment of risks and benefits of the investigated methods.

Technology and product ramp up suffers increasingly from systematic production defects. Diagnosis of scan test fail data plays an important role in yield enhancement as diagnosis of scan fail data helps to understand and overcome systematic production defects. Acquisition of scan fail data during high-volume production can lead to significant test time overhead. This paper presents a new on-chip architecture that evaluates scan test results and stores relevant scan diagnosis information on chip. Scan diagnosis data can be accessed after the scan test has finished with very little test time overhead. Moreover, the proposed technique is ATE independent. An implementation example, based on a state-of-the-art SoC device, is reported

This paper addresses delay test for SOC devices with high frequency clock domains. A logic design for on-chip high-speed clock generation, implemented to avoid expensive test equipment, is described in detail. Techniques for on-chip clock generation, meant to reduce test vector count and to increase test quality, are discussed. ATPG results for the proposed techniques are given.

This paper addresses delay test for SOC devices on low-cost testers. The case study focuses on the at-speed testing for a state-of the-art microcontroller device by using an on-chip high-speed clock generator. The experimental results show that the simple on-chip high-speed clock generator is not sufficient to reach both high fault coverage and acceptable pattern count. Meanwhile, at-speed test constraints, required to enable the delay test on low cost testers, have a significant impact on test generation results. DFT techniques to increase fault coverage and to reduce pattern count are discussed.