Article Incremental tree height reduction for high level synthesis Share on Authors: Alexandru Nicolau Information and Computer Science Department, University of California, Irvine, CA Information and Computer Science Department, University of California, Irvine, CAView Profile , Roni Potasmann Dept. of Electrical and Computer Engineering, University of California, Irvine, CA Dept. of Electrical and Computer Engineering, University of California, Irvine, CAView Profile Authors Info & Claims DAC '91: Proceedings of the 28th ACM/IEEE Design Automation ConferenceJune 1991 Pages 770–774https://doi.org/10.1145/127601.127767Published:01 June 1991 59citation307DownloadsMetricsTotal Citations59Total Downloads307Last 12 Months3Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

A new approach called Percolation Based Synthesis for the scheduling phase of High Level Synthesis (HLS) is presented. We discuss some new techniques (which are implemented in our tools) for compaction of flow graphs beyond basic blocks limits, which can produce order of magnitude speed ups versus serial execution. Our algorithm applies to programs with conditional jumps, loops and multicycle pipelined operations. In order to schedule under resource constraints we start by first finding the optimal schedule (without constraints) and then add heuristics to map the optimal schedule onto the given system. We argue that starting from an optimal schedule is one of the most important factors in scheduling because it offers the user flexibility to tune the heuristics and gives him a good bound for the resource constrained schedule. This scheduling algorithm is integrated with synthesis tool which uses VHDL as input description and produces a structural netlist of generic register-transfer components and a unit based control table as output. We show that our algorithm obtains better results than previously published algorithms.