As semiconductor technology node advances, the number of parameters in the modern device compact model increases drastically. Manual extraction of these model parameters becomes not only tedious but also impossible, and the automatic method is strongly desired. Traditional black-box optimization suffers from poor scalability due to the curse of dimensionality, while deep learning–based methods typically require large amounts of training data. To address these challenges, we propose CDRPE: a combined deep learning and self-attention enhanced reinforcement learning framework for automatically extracting a large set of DCM parameters across multiple electrical characteristics. The framework leverages a pre-trained multilayer perceptron to initialize core parameters, incorporates device physics knowledge to guide the search, and employs a self-attention–enhanced RL agent for efficient exploration in high-dimensional parameter spaces. Experimental results on BSIM4, BSIMSOI, and BSIMCMG demonstrate that CDRPE can automatically extract 100 parameters with root-mean-square error below 5% relative to TCAD and silicon data. Compared with existing methods, the proposed framework achieves a 7.7x speed up. Moreover, the generated models show good convergence in both digital and analog circuit simulations, exhibiting the potential of this framework for future practical applications.

Design automation of complex analog circuits (CAC) with multiple sub-blocks is challenging mainly due to large design search space, uncertain intermediate subgoal creation, and lengthy CAC simulation runtime. In this work, we propose a hierarchical and heterogeneous integration framework as a fully automated and time-efficient CAC design optimization solution. In Particularly, we (i) decompose CAC into two levels hierarchically and for the first time introduce hierarchical RL agents with hindsight and subgoal testing to automate the subgoal creation between these two levels. The subgoal converges to the optimal value through algorithm interactions. (ii) We enable high-level design space dimensionality reduction, minimize CAC simulation runs through a buffer hold, and employ low-level sub-block execution parallelization to reduce overall runtime. (iii) We construct a heterogeneous integration of different RL algorithms and black-box optimization algorithms in hierarchy to further boost the speed by benefiting both from the hierarchical structure and the advantages of each different algorithm. Experiments on four CAC topologies demonstrate that this framework achieves a maximum of 11.4× speed up compared to existing methods at the desired figure-of-merit. This work opens up a time efficient design automation route for complex analog circuits and systems.

For analog circuit sizing, constrained multi-objective optimization is an important and practical problem. With the popularity of multi-core machines and cloud computing, parallel/batch computing can significantly improve the efficiency of optimization algorithms. In this paper, we propose an Asynchronous Batch Constrained Multi-Objective Bayesian Optimization algorithm (ABCMOBO). Since the performances below the specifications are worthless, we adopt a dynamic reference point selection on the expected hypervolume improvement acquisition function for constraint handling. To save the time of waiting for all the simulations in the same batch to complete, ABCMOBO asynchronously evaluates the next candidate point if there is an idle worker. The experimental results quantitatively demonstrate that our proposed algorithms can reach 3.49 ~ $8.18 \times$ speed-up with comparable optimization results compared to the state-of-the-art asynchronous/synchronous batch multi-objective optimization methods.

Automated analog circuit design migration significantly alleviates the burden on designers in circuit sizing under various operating conditions. Conventional methods model the migration problem as black-box optimization, requiring excessive iterations of costly simulations to converge. Reinforcement learning exhibits significant promise in transfer learning, as it enables the generation of circuits that fulfill specifications efficiently. The paper proposes a novel value decomposition-based multi-agent reinforcement learning framework, aiming to model complex analog circuits and eliminate the need for manually defined specifications of sub-circuits for new operating conditions. Additionally, it incorporates domain randomization techniques to efficiently generate circuits that meet unforeseen scenarios with minimal simulations. Experiment demonstrates that our algorithm can efficiently generate circuits meeting specifications under new operating conditions in few number of steps, outperforming state-of-the-art methods.

Despite the effort of analog circuit design automation, currently complex analog circuit design still requires extensive manual iterations, making it labor intensive and time-consuming. Recently, reinforcement learning (RL) algorithms have been demonstrated successfully for the analog circuit design optimization. However, a robust and highly efficient RL method to design analog circuits with complex design space has not been fully explored yet. In this work, inspired by multiagent planning theory as well as human expert design practice, we propose a multiagent based RL (MA-RL) framework to tackle this issue. Particularly, we (i) partition the complex analog circuits into several sub-blocks based on topology information and effectively reduce the complexity of design search space; (ii) leverage MA-RL for the circuit optimization, where each agent corresponds to a single sub-block, and the interactions between agents delicately mimic the best design tradeoffs between circuit sub-blocks by human experts; (iii) introduce and compare three different multiagent RL algorithms and corresponding frameworks to demonstrate the effectiveness of the MA-RL method. (iv) employing twin-delayed techniques and proximal policy to further boost training stability and accomplish higher performances. (v) The impacts of different reward function definitions as well as different state settings of MA-RL agents are investigated to further improve the robustness of this framework. (vi) Experiments on three different complex analog circuit topologies (GBA, DLL and SAR ADC) and knowledge transfers between two technology nodes are demonstrated. It’s shown that MA-RL framework can achieve the best FoM for complex analog circuits’ design. This work shines the light for future large scale analog circuit system design automation.

Despite the effort of analog circuit design automation, currently complex analog circuit design still requires extensive manual iterations, making it labor intensive and time-consuming. Recently, reinforcement learning (RL) algorithms have been demonstrated successfully for the analog circuit design optimization. However, a robust and highly efficient RL method to design analog circuits with complex design space has not been fully explored yet. In this work, inspired by multiagent planning theory as well as human expert design practice, we propose a multiagent based RL (MA-RL) framework to tackle this issue. Particularly, we (i) partition the complex analog circuits into several sub-blocks based on topology information and effectively reduce the complexity of design search space; (ii) leverage MA-RL for the circuit optimization, where each agent corresponds to a single sub-block, and the interactions between agents delicately mimic the best design tradeoffs between circuit sub-blocks by human experts; (iii) introduce the multiagent twin-delayed techniques to further boost training stability and accomplish higher performances. Experiments on two different analog circuit topologies and knowledge transfers between two technology nodes are demonstrated. It’s shown that MA-RL framework can achieve the best FoM for complex analog circuits design. This work shines the light for future large scale analog circuit system design automation.

We propose a new technology and design platform using combined common gate (CG) N/PFET complementary field-effect transistor (CFET) as basic element for CMOS circuit applications. Two CFET unit structures, namely, CG and N-gate (NG), are identified to form base design elements. Through the two units, all circuit logic functions in standard cell library and SRAM can be realized without significant process complication. A multigradient neural network (MNN)-based SPICE compact modeling methodology is developed for these CFET units. As an example, MNN model generation is illustrated for CG with the output matching well with the TCAD data within and beyond the range of model extraction. Circuit simulations are exercised using the MNN models and demonstrated successfully the expected circuit functionalities. As the CFET technology be adopted as mainstream in future, this novel design framework proposed would enable efficient logic design.