Malicious applications, malware, continue to be a major security threat for computer systems. Due to the fast growing number and increasing complexity of malware, manual analysis became impractical and automated methods are preferred by security analysts. The automated dynamic analysis of malware executes the samples in controlled environments and monitors the execution for potentially malicious behavior. The vulnerability of this method is that modern malware detect these emulated or virtualized environments and suspend their malicious activities to foil the analysis. However, the malware exhibit a semantically different behavior when running directly on computer system hardware, i.e. bare-metal systems. Consequently, the ultimate technique for analyzing the behavior of malware is through execution of the samples in bare-metal analysis environments. Nevertheless, restoring the system to a clean state after each sample analysis is challenging. In order to restore the storage device state of a bare-metal system to a clean state, in this paper we propose an FPGA-implemented storage mirroring technique for instantaneous restoration of the storage device and, optionally, the retrieval of the files having been modified during the sample execution. The FPGA-based system can be integrated in commodity computer systems with Serial ATA storage devices. The retrieval of modified files is supported for systems running Windows operating systems with NTFS file-system. The experimental results demonstrate the viability of the solution.

An increasing number of high performance computing applications developed on reconfigurable platforms require access to mass storage devices for storing a large amount of data. The multi-gigabit transceivers integrated in FPGA devices allow the development of a wide range of communication protocols. The Serial ATA protocol provides a solution for accessing mass storage devices at high transfer rates. This paper describes the design and implementation of Serial ATA Gen3 Host and Device controllers on Xilinx 7-Series FPGA devices to facilitate the access of high performance and embedded applications to non-volatile storage devices, e.g. hard disk drives and solid state drives. The controllers can interface with commodity Serial ATA Gen3 storage devices and host bus adapters at a data transfer rate of 6.0 Gbps. For an increased performance, both Host and Device controllers support the Native Command Queueing (NCQ) feature set, in addition to the regular read and write commands. The experimental results demonstrate the viability of the Serial ATA Gen3 controllers and prove a sustained throughput close to the maximum theoretical data transfer rates of the Serial ATA protocol, thus having the potential of being an important building block of complex systems targeting a wide range of applications.

The subject of the article concerns a constrained predictive control with feedback linearization (FBL) applied for multiple-input and multiple-output (MIMO) system. It relies on finding a compromise in every step between feasible and optimal linear quadratic (LQ) control by minimization of one variable. Behaviour of model signals in function of minimized variable is investigated, in order to assure the optimality of the solution. LQ control based applications for feedback linearized models do not meet the problem of choosing weights in linear quadratic cost function. That important problem is solved here by comparison of the cost function with that obtained for the linear approximated system in the operating point. That provides satisfactory behaviour and also justifies the simplified approach relied on minimization of only one variable for MIMO system.

This paper presents the hardware implementation of the widely known NIST Statistical Test Suite - a battery of statistical tests for pseudorandom number generators (PRNGs) and true random number generators (TRNGs) - in a single Xilinx FPGA chip, using dynamic partial reconfiguration. The design offers a basic framework for easy integration of any additional randomness evaluation tests as well. Due to the integration of both the TRNG and the tests suite in a single FPGA chip, our solution offers new opportunities in the area of random number generation and testing, greatly reducing the time between the generation and the validation of the generated sequences of random bits.

In this paper, we describe our work in developing an agent based smart house platform using TAOM4E development methodology and the JADE-platform with the Jadex-extension. In order to remotely monitor its functions we implemented a Jade-Leap mobile application. We developed a central ontology for context representation and the support for behavior changes according to user's affective feedback. We also emphasize the issues related to ontologies supporting agent communication, sensor integration and affective sensing. Experimental results have showed the proper functioning of this system, whose novelty consists in merging together a multi-agent system, an ontology-based mixed environment representation and reasoning engine, and a rule-based model of the user's affective feedback.