Three-dimensional integration circuit (3D IC) offers significant benefits in terms of performance and cost. Existing research in through-silicon via (TSV)-based 3D IC partitioning has focused on minimizing the number of TSVs to reduce costs. Partitioning methods based on heterogeneous integration have emerged as viable approaches for cost optimization. Leveraging mature processes to manufacture not timing-critical blocks can yield cost benefits. Nevertheless, none of the previous 3D partitioning work has focused on reducing the overall cost, including both design and manufacturing costs, for heterogeneous 3D integration. Moreover, throughput constraints have not been considered. This article presents a cost-aware integer linear programming-based formulation and a heuristic algorithm that partition the functional blocks in the design into different technological groups. Each group of functional blocks will be implemented using a particular process technology, and then integrated into a 3D IC. Our results show that 3D heterogeneous integration chip implementation can reduce overall cost while satisfying various timing constraints.

Multiprocessor system-on-chips (MPSoCs) in modern devices have mostly adopted the non-uniform cache architecture (NUCA) [1], which features varied physical distance from cores to data locations and, as a result, varied access latency. In the past, researchers focused on minimizing the average access latency of the NUCA. We found that dynamic latency is also a critical index of the performance. A cache access pattern with long dynamic latency will result in a significant cache performance degradation without considering dynamic latency. We have also observed that a set of commonly used neural network application kernels, including the neural network fully-connected and convolutional layers, contains substantial accessing patterns with long dynamic latency. This paper proposes a hardware-friendly dynamic latency identification mechanism to detect such patterns and a dynamic link-latency aware replacement policy (DLRP) to improve cache performance based on the NUCA.

We propose a cache architecture using a 7T/14T SRAM (Fujiwara et al., 2009) and a control mechanism for reliability enhancements. Our control mechanism differs from conventional dynamic voltage-frequency scaling (DVFS) methods in that it considers not only the cycles per instruction behaviors but also the cache utilization. To measure cache utilization, a novel metric is proposed. The experimental results show that our proposed method achieves 1000 times less bit-error occurrences compared with conventional DVFS methods under the ultralow-voltage operation. Moreover, the results indicate that our proposed method surprisingly not only incurs no performance and energy overheads but also achieves on average a 2.10% performance improvement and a 6.66% energy reduction compared with conventional DVFS methods.

Significant advances in very large-scale integration process technology have scaled the feature size down. One effect of this scaling down is that coupling capacitances have grown reciprocal in the square of the scaling factor. This crosstalk effect will not only increase the power consumption but also lengthen the propagation delay. Since the data sequences on an instruction bus are known during the compile time, this paper presents two compiler algorithms, rescheduling and renaming, for performance improvement by eliminating crosstalk effects on an instruction bus. The results show that our crosstalk-eliminating postcomplier algorithms significantly reduce the dynamic instruction overhead from 11.50% to 0.52% by eliminating the 4middotC crosstalk. Due to the effective 4middotC crosstalk elimination, our proposed method can improve the instruction fetch time up to 9.59%

Significant advances in VLSI process technology have scaled the feature size down. One effect of this scaling down is that coupling capacitances have grown reciprocal in the square of the scaling factor. This crosstalk effect will not only increase the power consumption but also lengthen the propagation delay. Since the data sequences on an instruction bus are known during the compile time, this paper presents two post-compiler algorithms, rescheduling and renaming, for performance improvement by eliminating crosstalk effects on an instruction bus. The results show that our crosstalk-eliminating post-complier algorithms significantly reduce the dynamic instruction overhead from 11.50% to 0.52% by eliminating the 4-C crosstalk. Due to the effective 4-C crosstalk elimination, our proposed method can improve the instruction fetch time up to 9.59%.

During the execution of processor instruction, decoding the instructions is a major task in identifying instructions and generating control signals for data paths. In this article, we propose two instruction decoder decomposition techniques for low-power designs. First, by tracing program execution sequences, we propose an algorithm that explores the relations between frequently executed instructions. Second, we propose a two-stage low-power decomposition structure for decoding instructions. Experimental results demonstrate that our proposed techniques achieve an average of 34.18% in power reduction and 12.93% in critical-path delay reduction for the instruction decoder.

This paper presents a novel power-driven multiplication instruction-set design method for application-specific instruction-set processors (ASIPs). Based on a dual-and-configurable-multiplier structure, our proposed method devises a multiplication instruction set for low-power ASIPs. Our method exploits the execution sequences of multiplication instructions and effective bit widths of variables to reduce power consumed by redundant multiplication bits while minimizing the multiplication execution time. Experimental results on a set of DSP programs demonstrate that our proposed method achieves significant power reduction (up to 18.53%) and execution time improvement (up to 10.43%) with 18% area overhead.

Microprocessors have been used in wide-ranged applications.During the execution of instructions, instruction decoding is a major task for identifying instructions and generating control signals for data-paths.By exploiting program behaviors, we propose a novel instruction-decoding approach for power minimization.Using the proposed instruction-decoding structure, we present a partitioning method that decomposes the instruction-decoding circuit into two sub-circuits according to the execution frequencies of instructions.Using our proposed decoding structure, only one sub-circuit will be activated when executing an instruction.Experimental results have demonstrated that our proposed approach achieves on an average of 26.71% and 15.69% power reductions for the instruction decoder and the control unit, respectively.

Article Free Access Share on Embedded tutorial: essential issues for IP reuse Authors: Daniel D. Gajski University of California, Irvine University of California, IrvineView Profile , Allen C.-H. Wu Tsing Hua University, Taiwan, ROC Tsing Hua University, Taiwan, ROCView Profile , Viraphol Chaiyakul Y Explorations Inc. Y Explorations Inc.View Profile , Shojiro Mori Toshiba Corp., Japan Toshiba Corp., JapanView Profile , Tom Nukiyama NEC Corp., Japan NEC Corp., JapanView Profile , Pierre Bricaud Mentor Graphics Corp. Mentor Graphics Corp.View Profile Authors Info & Claims ASP-DAC '00: Proceedings of the 2000 Asia and South Pacific Design Automation ConferenceJanuary 2000 Pages 37–42https://doi.org/10.1145/368434.368504Published:28 January 2000Publication History 19citation399DownloadsMetricsTotal Citations19Total Downloads399Last 12 Months37Last 6 weeks3 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

In this paper, we present an RTL delay-budgeting approach for a timing-closure-driven design method. We formulate the delay-budgeting problem into the Lagrange-Multipliers-based slack distribution problem. We present two algorithms, namely the balanced slack distribution algorithm and the AT-based (Area-Time) slack distribution algorithm, to solve the problem. We also present a timing-closure-driven design flow by integrating commercial synthesis/layout tools with the proposed algorithms. We have demonstrated the viability of the proposed RTL delay-budgeting method. The results show that without an accurate AT-characteristic projection of modules the balanced slack distribution algorithm will be a good choice for delay budgeting at RTL.

In this paper, we present a new integrated synthesis and partitioning method for multiple-FPGA applications. Our approach bridges the gap between HDL synthesis and physical partitioning by fully exploiting the design hierarchy. We propose a novel multiple-FPGA synthesis and partitioning method which is performed in three phases: (1) fine-grained synthesis, (2) functional-based clustering, and (3) hierarchical set-covering partitioning. This method first synthesizes a design specification in a fine-grained way so that functional clusters can be preserved based on the structural nature of the design specification. Then, it applies a hierarchical set-covering partitioning method to form the final FPGA partitions. Experimental results on a number of benchmarks and industrial designs demonstrate that I/O limits are the bottleneck for CLB utilization when applying a traditional multiple-FPGA synthesis method on flattened netlists. In contrast, by fully exploiting the design structural hierarchy during the multiple-FPGA partitioning, our proposed method produces fewer FPGA partitions with higher CLB and lower I/O-pin utilizations.

This paper presents a system-level power management technique for energy savings of event-driven application. We present a new predictive system-shutdown method to exploit sleep mode operations for energy saving. We use an exponential-average approach to predict the upcoming idle period. We introduce two mechanisms, prediction-miss correction and prewake-up, to improve the hit ratio and to reduce the delay overhead. Experiments on four different event-driven applications show that our proposed method achieves high hit ratios in a wide range of delay overheads, which results in a high degree of energy with low delay penaties.

Converting an HDL-based design into an emulation system for design verification is an extremely complex and time-consuming task. One possible solution to improve productivity is an effective emulation-based design methodology that exploits the modularity of designs. This paper develops and explores such a methodology. We present a multi-level synthesis method which is able to establish a direct link between High-level Descriptive Language (HDL) constructs and corresponding circuit designs. This feature greatly facilitates HDL debugging capabilities such that when bugs are detected in sub-netlists, links allow the corresponding HDL source code to be easily recognized. This powerful feature greatly reduces design debugging time. Experimental results on a set of industrial designs are reported in order to demonstrate the effectiveness of the proposed synthesis methodology.

In this paper, we present a complete chip design method which incorporates a soft-macro resynthesis method in interaction with chip oorplanning for area and timing improvements.We develop a timing-driven design ow to exploit the interaction between HDL synthesis and physical design tasks.During each design iteration, we resynthesize soft macros with either a relaxed or a tightened timing constraint which is guided by the post-layout timing information.The goal is to produce area-ecient designs while satisfying the timing constraints.Experiments on a number of industrial designs have demonstrated that by eectively relaxing the timing constraint of the non-critical modules and tightening the timing constraint of the critical modules, a design can achieve 13% to 30% timing improvements with little to no increase in chip area.

No abstract available.

In this paper, we present a complete chip design method which incorporates a soft-macro placement and resynthesis method in interaction with chip floorplanning for area and timing improvements. We present a performance-driven soft-macro clustering and placement method which preserves hardware descriptive language (HDL) design hierarchy to guide the soft-macro placement process. We develop a timing-driven design flow to exploit the interaction between HDL synthesis and physical design tasks. During each design iteration, we resynthesize soft macros with either a relaxed or a tightened timing constraint which is guided by the post-layout timing information. The goal is to produce area-efficient designs while satisfying the timing constraints. Experiments on a number of industrial designs ranging from 75-K to 230-K gates demonstrate that the proposed soft-macro clustering and placement method improves critical-path delays on an average of 22%. Furthermore, the results show that by effectively relaxing the timing constraint of noncritical modules and tightening the timing constraint of critical modules, a design can achieve 11% to 30% timing improvements with little to no increase in chip area.

Logic emulation is a technique that uses dynamically reprogrammable systems for prototyping and design verification. Using an emulator, designers can realize designs through a software configuration process and perform real-time design verification before fabricating the chip into silicon. However, converting designs into an emulator involves the use of multiphase design tasks, which is a very time-consuming process. Hence, shortening the time to emulation is always the main concern for the logic-emulation design process. One approach to shorten the design processing time is to replace portions of the design with macro cells. This paper presents a module generator for logic-emulation applications, which is able to generate macro cells of arbitrarily complex functions described in hardware descriptive languages. Furthermore, the module generator can effectively generate a multiple field-programmable gate array (FPGA) macro for large macros that cannot fit in a single FPGA chip. Experiments using the module generator for logic emulation are reported. The results demonstrate that the module generator can effectively and efficiently generate complex macros from their register transfer-level description. In addition, the results also show that the design processing time is significantly shortened when the module generation method is incorporated into the logic-emulation design flow.

This paper presents a new performance-driven partitioning method for multi-FPGA designs. The proposed methodconsists of three steps: #1# functional-cluster formation, #2# slack computation, and #3# set-coveringbasedpartitioning with functional replication. The proposed methodperforms multi-FPGA partitioning by taking into account path delays and design structural information. We introduce a functional replication technique which performs circuit replications at the functionalcluster level instead of the cell level for delay and interconnect minimization. Experimental results on a number of benchmarks and industrial designs demonstrate that the proposed method achieves high-performance and high-density multi-FPGA partitions. 1 Introduction In general, the traditional HDL-based design #ow from initial speci#cation to multiple-FPGA systems consists of two independent design phases. In the #rst phase, a synthesizer is used to transform an HDL design speci#cation into a CLB-based netlist....

In this paper, we present a performance-driven soft-macro clustering and placement method which preserves HDL design hierarchy to guide the soft-macro placement process. We also present a complete chip design methodology by integrating the proposed method and a set of commercial EDA tools. Experiments on three industrial designs ranging from 75K to 230K gates demonstrate that the proposed soft-macro clustering and placement method improves critical-path delay on an average of 24%.

Presents a datapath generator for multiple-FPGA applications. This datapath generator is able to generate complex datapath designs described in HDLs. Our datapath generator uses a novel synthesis and partitioning approach which bridges the gap between RTL/logic synthesis and physical partitioning to fully exploit the design structural hierarchy for multiple-FPGA implementations. Experiments on a number of benchmarking circuits and industry designs demonstrate that the generator can effectively and efficiently produce high-density multiple-FPGA datapaths.

In this paper, we present a study on the relationship between entropy and the average power consumption, of circuits generated from Boolean functions. Based on a general-delay model, an entropy-based formulation for power estimation is derived from a large set of experimental data. The study shows that the entropy measure provides an effective power estimate for single-output and fully-correlated multiple-output functions. The study also shows that if entropy is used as a power measure, the internal structure of a circuit must be considered in order to achieve accurate power estimates for non-correlated multiple-output functions. Experiments on a set of benchmarks demonstrate that combining entropy-based power measures with input-output correlation analyses of logic functions leads to a viable measure for high-level power estimation.

Evaluation of design cost and performance is indispensable to system partitioning. In the absence of a system-level estimation and analysis tool, system partitioning is difficult to perform in an efficient and accurate manner because design evaluation can only be done after the final results are achieved. Furthermore, without cost-performance tradeoff information relating to different design alternatives, the designer can not make intelligent design decisions at the early system-level partitioning stages. In this paper, we present a system-level cost/performance evaluation approach which systematically explores the AT (Area-Time) design-space from a system description. This allows the designer to obtain first-hand design tradeoff information before the partitioning process has taken place. We have also developed a system-level interactive design evaluation system on top of the proposed approach. Experiments on a number of examples demonstrate that our approach provides the designer with a comprehensive system-level design evaluation method to effectively explore all possible design, alternatives in the early stages of system development.

In this paper, we present a new integrated synthesisand partitioning method for multiple-FPGA applications.This method first synthesizes a design specificationin a fine-grained way so that functional clusters can bepreserved based on the structural nature of the designspecification.Then, it applies a hierarchical set-coveringpartitioning method to form the final FPGA partitionings.Our approach bridges the gap between HDL synthesisand physical partitioning by fully exploiting the designhierarchy.Experimental results on a number of benchmarksand industrial designs demonstrate that I/O limitsare the bottleneck for CLB utilization when applying atraditional multiple-FPGA synthesis method on flattenednetlists.In contrast, by fully exploiting the design structuralhierarchy during the multiple-FPGA partitioning,our proposed method produces fewer FPGA partitionswith higher CLB and low I/O-pin utilizations.

In recent years, logic emulation has been widely usedas a key design verification methodology in many complex CPU, telecom, and multimedia design projects. When using logic emulation for design verification, designers often need toperform engineering changes as a result of design debugging of a design specificationmodification. One of the essential issues to engineeringchanges is the turn-around time. Ideally, after designers modify their designs, they resume their debugging and verification tasks immediately. However, converting a design from its Register-Transfer-Level (RTL) description to a target emulator is a time-consuming procedure which may take hours. Such long engineering-change turn-around times are unacceptable by the designers. In this paper, we present a real-time RTLengineering-change method supporting on-line debuggingfor logic-emulation applications. We propose a novel design method which is able to link design data generated at different design stages in a unified way. Using thismethod, the users can immediately locate the portion ofthe circuit design affected by the design modification fromits RTL specification. This feature provides users with afast time-to-debug environment by significantly improving the efficiency of the engineering-change process. We have developed aprototype system Quick ECO supporting interactive on-line RTL engineering changes. Experimental results on a number of industrial designs are reported to demonstrate the effectiveness of the proposed method.

Logic emulation is a technique that uses dynamically reprogrammable systems for prototyping and design verification. Using an emulator, designers can realize designs through a software configuration process and perform real-time design verification before fabricating the chip into silicon. However, converting designs into an emulator involves the use of multi-phase design tasks, which is a very time-consuming process. Hence, shortening the Time-To-Emulation (TTE) is always the main concern for the logic-emulation design process. One approach t o shorten the design processing time is to replace portions of the design with macro cells. This paper presents a module generator for logic-emulation applications, which is able to generate macro cells of arbitrarily complex functions described in High-level Descriptive Languages the (HDLs), Furthermore, the module generator can effectively generate a multiple-FPGA macro for large macros which can not fit in a single FPGA chip. Experiments using the module generator for logic emulation are reported. The results demonstrate that the module generator can effectively and efficiently generate complex macros from their Register-Transfer-Level (RTL) description. In addition, the results also show that the design processing time is significantly shortened when the module generation method is incorporated into the logic-emulation design flow.

We present a system-level power management technique for power saving of event-driven applications. We present a new predictive system shutdown method to exploit sleep mode operations for power saving. We use an exponential-average approach to predict the upcoming idle period. We introduce two mechanisms, prediction-miss correction and pre-wakeup, to improve the hit ratio and to reduce the delay overhead. Experiments on four different event-driven applications show that our proposed method achieves high hit ratios in a wide range of delay overheads, which results in a high degree of power saving with low delay penalties.

Article Preserving HDL synthesis hierarchy for cell placement Share on Authors: Yu-Wen Tsay Department of Computer Science, Tsing Hua University, Hsinchu, Taiwan, 300, Republic of China Department of Computer Science, Tsing Hua University, Hsinchu, Taiwan, 300, Republic of ChinaView Profile , Wen-Jong Fang Department of Computer Science, Tsing Hua University, Hsinchu, Taiwan, 300, Republic of China Department of Computer Science, Tsing Hua University, Hsinchu, Taiwan, 300, Republic of ChinaView Profile , Allen C.-H. Wu Department of Computer Science, Tsing Hua University, Hsinchu, Taiwan, 300, Republic of China Department of Computer Science, Tsing Hua University, Hsinchu, Taiwan, 300, Republic of ChinaView Profile , Youn-Long Lin Department of Computer Science, Tsing Hua University, Hsinchu, Taiwan, 300, Republic of China Department of Computer Science, Tsing Hua University, Hsinchu, Taiwan, 300, Republic of ChinaView Profile Authors Info & Claims ISPD '97: Proceedings of the 1997 international symposium on Physical designApril 1997 Pages 169–174https://doi.org/10.1145/267665.267709Online:01 April 1997Publication History 6citation193DownloadsMetricsTotal Citations6Total Downloads193Last 12 Months0Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

In this short paper, we present a new integrated synthesis and partitioning approach for multiple-field programmable interconnect chips (FPICs) implementations from register-transfer (RT) netlists. Our approach bridges the gap between RTL/logic synthesis and physical partitioning by finely tuning logic implementations suited for multiple-FPGA systems. We propose a hierarchical functional structuring and partitioning method which fully exploits the design structural hierarchy by decomposing RTL components into sets of logic subfunctions. This allows the partitioner to place portions of components into FPGA partitions. Experimental results on a number of benchmarks and industrial designs show that our approach achieves significant improvement in FPGA configurable logic block (CLB) and I/O-pin utilizations compared to that produced using a traditional multiple-FPGA partitioning method.

This paper presents a new performance and routability driven router for symmetrical array based field programmable gate arrays (FPGAs). The objectives of our proposed routing algorithm are two-fold: (1) improving the routability of the design (i.e., minimizing the maximum required routing channel density) and (2) improving the overall performance of the design (i.e., minimizing the overall path delay). Initially, nets are routed sequentially according to their criticalities and routabilities. The nets/paths violating the routing-resource and timing constraints are then resolved iteratively by a rip-up-and-rerouter, which is guided by a simulated evolution based optimization technique. The proposed algorithm considers the path delays and routability throughout the entire routing process. Experimental results show that our router can significantly improve routability and reduce delay over many existing routing algorithms.

This paper presents an integer linear programming (ILP) model and a heuristic for the variable voltage scheduling problem. We present the variable voltage scheduling techniques that consider in turn timing constraints alone, resource constraints alone, and timing and resource constraints together for design space exploration. Experimental results show that our heuristic produces results competitive with those of the ILP method in a fraction of the run-time. The results also show that a wide range of design alternatives can be generated using our design space exploration method. Using different cost/delay combinations, power consumption in a single design can differ by as much as a factor of 6 when using mixed 3.3V and 5V supply voltages.

We present a new synthesis and partitioning approach for multiple-FPGA implementations from register-transfer-level (RTL) netlists. Our approach bridges the gap between RTL/logic synthesis and physical partitioning by finely tuning logic implementations suited for multiple-FPGA systems. We propose a hierarchical functional structuring and partitioning method which fully exploits the design structural hierarchy by decomposing RTL components into sets of logic sub-functions. This allows the partitioner to place portions of components into FPGA partitions. Experimental results on a number of benchmarks and industrial designs show that our approach achieves significant improvements in CLB and IO-pin utilizations of FPGAs compared to that produced using a traditional multiple-FPGA partitioning method.

This paper presents a cooperative design-view environment for interactive partitioning applications. This environment provides the user with a comprehensive viewing facility that describes the potentially complex relationships between various design objects. Using this environment, the user is able to evaluate and analyse design results visually throughout the entire partitioning process. We have developed a graphical user interface (GUI) environment for the InterPar system which supports mixed automatic and manual partitioning for multiple-field programmable gate array (FPGA) designs. The preliminary experiments have shown that the use of InterPar may lead to a new direction for the exploration of new partitioning approaches based on the circuit-structure analysis.

No abstract available.

Article A performance and routablity driven router for FPGAs considering path delays Share on Authors: Yuh-sheng Lee Department of Computer Science, Tsing Hua University, Hsin-Chu, Taiwan 30043, R.O.C. Department of Computer Science, Tsing Hua University, Hsin-Chu, Taiwan 30043, R.O.C.View Profile , Allen C.-H. Wu Department of Computer Science, Tsing Hua University, Hsin-Chu, Taiwan 30043, R.O.C. Department of Computer Science, Tsing Hua University, Hsin-Chu, Taiwan 30043, R.O.C.View Profile Authors Info & Claims DAC '95: Proceedings of the 32nd annual ACM/IEEE Design Automation ConferenceJanuary 1995 Pages 557–561https://doi.org/10.1145/217474.217588Online:01 January 1995Publication History 30citation177DownloadsMetricsTotal Citations30Total Downloads177Last 12 Months1Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

We describe a routing method for the design of a class of RAM-based field programmable gate arrays (FPGA). We model the interconnect resources as a graph. A routing solution is represented as a set of disjoint trees, each connecting all terminals of a net, on the graph. An expansion router is used for connecting a net. Initially, nets are connected independently of one another. Conflicts among nets over the usage of interconnect resources are resolved iteratively by a rip-up and rerouter, which is guided by a simulated evolution-based optimization technique. The proposed approach has been implemented in a program called TRACER-fpga. As compared with CGE and SEGA, TRACER-fpga in general requires fewer routing tracks at the expense of longer wiring delay. It is suitable for low-speed applications such as hardware emulation.>

We combine technology mapping and placement into a single procedure, M.Map, for the design of RAM-based FPGAs. Iteratively, M.Map maps several subnetworks of a Boolean network into a number of CLBs on the layout plane simultaneously. For every output node of the unmapped portion of the Boolean network, many ways of mapping are possible. The choice of which mapping to be used depends not only on the location of the CLB into which the output node will be mapped but also on its interconnection with those already mapped CLBs. To deal with such a complicated interaction among multiple output nodes of a Boolean network, multiple ways of mappings and multiple number of CLBs, any greedy algorithm will be insufficient. Therefore, we use a bipartite weighted matching algorithm in finding a solution that takes the global information into consideration. With the availability of the partial placement information, M.Map is able to minimize the routing delay in addition to the number of CLBs. Experimental results on a set of benchmarks demonstrate that M.Map is indeed effective and efficient.>

We address the problem of state assignment to minimize both area and power dissipation for finite state machine designs. We propose a new matching-based state-assignment algorithm which considers area and state transitions simultaneously. Experimental results on a set of benchmarks demonstrate that our approach is indeed very effective in minimizing both area and power dissipation.>

We propose a transformation-based scheduling algorithm for the problem given a loop construct, a target initiation interval and a set of resource constraints, schedule the loop in a pipelined fashion such that the iteration time of executing an iteration of the loop is minimized. The iteration time is an important quality measure of a data path design because it affects both storage and control costs. Our algorithm first performs an As Soon As Possible Pipelined (ASAPp) scheduling regardless the resource constraint. It then resolves resource constraint violations by rescheduling some operations. The software system implementing the proposed algorithm, called Theda.Fold, can deal with behavioral loop descriptions that contain chained, multicycle and/or structural pipelined operations as well as those having data dependencies across iteration boundaries. Experiment on a number of benchmarks is reported.>

We combine technology mapping and placement into a single procedure, M.map, for the design of RAM-based FPGAs. Iteratively, M.map maps several subnetworks of the Boolean network into a number of CLBs on the layout plane simultaneously. For every output node of the un-mapped portion of the Boolean network, many ways of mapping are possible. The choice depends on the location of the CLB into which the output node will be mapped as well as the interconnection with those already mapped CLBs. To deal with such a complicated interaction among multiple output nodes, multiple ways of mappings and multiple CLBs, any greedy algorithms will be insufficient. Instead, we use a bipartite weighted matching algorithm to find a globally optimum solution. With the availability of the partial placement information. M.map is able to minimize the routing delay in addition to the number of CLBs. Experimental results on a set of benchmarks demonstrate that M.map is indeed very effective in minimizing the real delay (after routing) as well as the number of CLBs.

The problem of scheduling a loop in a pipelined fashion such that the iteration time (turnaround time) is minimized, given a loop behavior, a target initiation interval, and resource constraints, is considered. The iteration time is an important quality measure of a data path design because of its direct correlation with both the storage and the control costs. The scheduler starts with performing as-soon-as-possible-pipelined (ASAP/sub p/) scheduling without regard to the resource constraint. It then resolves the resource constraint violations, if there are any, by repeatedly rescheduling some operations.>

The problem of estimating design quality measures to accurately reflect design tradeoffs and efficiently explore the design space is discussed. Specifically, interest is centered on predicting the layout area and delay of a given structural RT level design. Clearly, current RT level cost measures are highly simplified and do not reflect the real physical design. In order to establish a more realistic assessment of layout effects, a layout model which accurately and efficiently accounts for the effects of wiring and floorplanning on the area and performance layout of RT level designs is proposed. Benchmarking has shown that this model is quite accurate.>

An efficient multiview design model for real-time interactive synthesis of behavioral descriptions into layout data is described. A hybrid data structure which combines all of the design data needed throughout multiple levels of abstraction, including behavior, structure, and floorplan, into a single unified view is presented. A detailed time and space complexity analysis of the proposed design model is also given, showing that it provides fast updating capabilities for incremental design changes but does not require an exorbitant amount of memory space. These features make this design model ideal for user-controlled synthesis systems that support incremental design and redesign tasks. Furthermore, the simplicity of the data structure allows easy implementation, maintenance, and extensibility.>

The authors define a new, sliced layout architecture for compilation of arbitrary schematics (netlists) into layout for CMOS technology. This sliced architecture uses over-the-cell routing on the second metal layer. The authors define three different architectures with simple folding, interleaved folding, and unrestricted folding and give algorithms for optimizing the layout area for several variants of the selected architecture. A proof demonstrating that the architecture with interleaved folding is as good as the architecture with unrestricted folding with respect to area minimization of the total layout is given. The authors also present results of random benchmarks as well as several real benchmarks.>

A partitioning methodology that exploits the regularity of register-transfer components is presented, and partitioning algorithms that are used to generate the floor plan are described. The partitioning algorithms not only select the layout style best suited for each component, but also consider critical paths, I/O pin locations, and connections between components. This approach improves the overall area utilization and minimizes the wire length on the critical paths.>

The authors propose a novel layout area model for quality measures in high-level synthesis. The model is proposed for two commonly used datapath and control layout architectures. Except for macrocells (PLAs), the proposed models formulate layout area as a function of transistors and routing tracks which can be computed in O(n log n) time complexity, where n is the number of nets in the netlist. This allows one to explore design space in high-level synthesis rapidly and efficiently. The authors have tested their layout models on the widely used elliptic-filter benchmark. The results show that these models can more accurately predict layout areas than models based on the number and size of registers and multiplexers.>

A sliced-layout architecture is presented to alleviate the problems of the general bit-sliced layouts. Also described are partitioning algorithms that are used to generate the floorplan for this layout architecture. The partitioning algorithms not only select the best suited layout style for each component, but also consider critical paths, I/O pin locations, and connections between logic blocks. This approach improves the overall area utilization and minimizes the total wire length.>