Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data. A simulation from public publication records: the people listed were not invited and did not agree to review.
? Tutorial for this page

Kouichi Takemura

dblp:05/6254 · DBLP profile ↗
← Back
1ranked-venue papers
0as first author
0since 2021 · last 1991
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Computer networks · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer networks
1 paper
Routing and switching · 87% Network performance modeling · 13%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Routing and switching › switch architecture
packet switch architecture
0.011991
A High-Speed Packet Switch Architecture with a Multichannel Bandwidth Allocation · INFOCOM 1991
Routing and switching › packet switching
virtual circuit
0.011991
A High-Speed Packet Switch Architecture with a Multichannel Bandwidth Allocation · INFOCOM 1991
Network performance modeling › switch performance analysis
switching delay
0.011991
A High-Speed Packet Switch Architecture with a Multichannel Bandwidth Allocation · INFOCOM 1991

Methods — techniques the papers use, named apart from their topics

simulation · 0.0
YearPublicationVenuePosition
1991 A High-Speed Packet Switch Architecture with a Multichannel Bandwidth Allocation
abstract
A novel packet switch architecture is proposed based on a channel grouped virtual circuit (CG-VC) scheme for high-speed communication networks. The case is considered in which there are several parallel channels between two switching nodes. The CG-VC scheme allows a packet to select an available channel in such a way as to avoid congested channels using a simple, hardware-based, self-routing mechanism. As a result, the architecture provides efficient channel use and low switching delay. The performance of the proposed switch is evaluated by simulation. The results show the proposed switch significantly improves channel utilization and switching delay compared with conventional single-channel allocation transmission policies.>
Kazuhiro Ohtsuki, Kouichi Takemura, James F. Kurose, Hiromi Okada, Yoshikazu Tezuka
INFOCOM2