Emerging SDR baseband platforms are usually based on multiple DLP+ILP processors with massive parallelism. Although these platforms would theoretically enable advanced SDR signal processing, existing work implemented basic systems and simple algorithms. Importantly, MIMO is not fully supported in most implementations. Implemented MIMO but with a simple linear detector. Our work explores the feasibility for SDR implementations of soft-output ML MIMO detectors, which brings 6-12 dB SNR gains when compared to popular linear detectors. Although soft-output ML MIMO detectors are considered to be challenging even for ASICs, we combine architecture-friendly algorithms, application specific instructions, code transformations and ILP/DLP explorations to make SDR implementations feasible. In our work, a 2times4 ADRES based ASIP with 16-way SIMD can deliver 193 Mbps for 2times2 64 QAM, and 368 Mbps for 2times2 16 QAM transmissions. To the best of our knowledge, this is the first work exploring SDR based soft-output ML MIMO detectors.

Complex signal processing algorithms are often specified in floating point precision. Thus, a type conversion is needed when the targeted platform requires fixed-point precision. In this work we proposed a new method to evaluate the final impact of finite precision processing in wireless applications. The latter combines analytical analysis with simulations. This extends previous work including the effect of the decision-making errors resulting from quantization. Thereby efficient dimensioning of the minimum bit-widths that satisfy a given accuracy constraint can be deployed. The method is validated with two representative case studies, namely an OFDM inner receiver and a Near-ML MIMO (Multiple Inputs, Multiple Outputs) detector.

Software Defined Radio (SDR) terminals are crucial to enable seamless and transparent inter-working between fourth generation wireless access systems or communication modes. On the longer term, SDRs will be extended to become cognitive radios enabling efficient spectrum usage. Future communication modes will have heavy hardware resource requirements and switching between them will introduce dynamism in respect with timing and size of resource requests. In this paper, we propose a modeling framework that enables the simulation of such complex, dynamic hardware/software SDR designs. Thus, we can do an exploration, which can pinpoint the coarse grain platform component requirements for future SDR applications in a very early design phase. Our solution differs from existing ones by combining multiple simulation granularities in a way that is specialized for SDR simulation. Finally, we demonstrate the effectiveness of our approach with a case study for dimensioning the on-chip interconnect of a prospective SDR platform.

Wireless communication standards are continuously evolving and getting more diverse.This requires a wide variety of baseband implementations within a short time-to-market. Besides, deep sub-micron technology significantly increases the design complexity and associated cost. These yield a growing need for reconfigurable/programmable baseband solutions. Implementing the whole base band functionality on programmable architectures, as foreseen in the tier-2 SDR, will become a must. However, the energy efficiency of SDR baseband platforms is unavoidably worse than the ASIC counterparts. This brings a challenging gap to bridge, which is even broadening further in emerging high rate standards. With a holistic view, we advocate a system level algorithmic approach to bridge this gap. Specifically, we propose to leverage the advantages (programmability) of SDR platforms to compensate for its disadvantages (energy efficiency). Highly flexible baseband algorithms are designed to exploit the abundant dynamics in the environment and the user requirements.In this way, the baseband can utilize the dynamics and substantially reduce the average energy consumption. In this paper, we present a design methodology and principles, illustrated with 3 representative case studies in HSDPA, WiMAX, and 3GPP LTE.

It is widely acknowledged that three-dimensional (3-D) technologies offer numerous opportunities for system design. In recent years, significant progress has been made on these 3-D technologies, and they have become probably the best hope for carrying the semiconductor industry beyond the path of Moore's law. However, a clear roadmap is missing to successfully introduce this 3-D technology onto the market. Today, a plurality of 3-D technology options exists, which requires different design and test strategies. To crystallize the many technology options in a few mainstream technologies, it is mandatory to coexplore both technology and design options. The contribution of this paper is to introduce a novel path finding methodology to untangle the many intertwined design/technology options. This holistic approach will be applied on a representative 3-D case study. Initial results demonstrate the benefits of the proposed path-finding methodology to steer the technology development and fine-tune design strategies.

Nowadays, mobile devices are integrating an increasing variety of wireless communication standards, and each standard demands a multitude of modes. This tremendous diversity, combined with the increasing development-cost of deep-submicron silicon, desires highly flexible baseband implementations. The tier-2 SDR (Software Defined Radio) paradigm, where the entire baseband runs on programmable architectures, is very attractive to obtain the desired flexibility. Parallel ISP (Instruction Set Processor) based SDR baseband platforms have attracted extensive interest in recent years. However, such implementations typically come with a much lower energy-efficiency than traditional implementations as ASICs (Application Specific Integrated Circuits). This energy efficiency gap remains to be bridged in order to make SDR more pervasive. Importantly, the gap is becoming even more and more challenging in emerging high rate communication standards, such as 3GPP LTE, Mobile WiMAX and 802.11n. This situation demands disruptive innovations.

Summary form only given. 3D integration offers numerous opportunities for design, and is probably the best hope for carrying ICs along (and even beyond) the path of Moore's Law in the 21st century. However, many questions still need to be answered to take advantage of 3D. First, what will become the mainstream 3D technology? Today, many technology options are proposed, but each having different cost, design and test implications. Secondly, how to make 3D designs reliable? Many unknowns still exist related to thermal load, reliability and signal integrity challenges. Finally, what about design solutions/methods and architectural modifications for 3D integration? The objective of this special session is to create a better understanding of forthcoming 3D technologies, their implication on design and test. An attempt will be made to roadmap 3D technologies and their design implications. This will enable R&D planning by design houses, EDA vendors, foundries and academia, paving the way for a widespread acceptance of 3D technologies.

The software-defined radio (SDR) concept aims to enabling cost-effective multi-mode baseband solutions for wireless terminals. However, the growing complexity of new communication standards applying, e.g., multi-antenna transmission techniques, together with the reduced energy budget, is challenging SDR architectures. Coarse-grained array (CGA) processors are strong candidates to undertake both high performance and low power. The design of a candidate hybrid CGA-SEVID processor for an SDR baseband platform is presented. The processor, designed in TSMC 90 G process according to a dual-VT standard-cells flow, achieves a clock frequency of 400 MHz in worst case conditions and consumes maximally 310 mW active and 25 mW leakage power (typical conditions) when delivering up to 25,6 GOPS (16-bit). The mapping of a 20 MHz 2times2 MIMO-OFDM transmit and receive baseband functionality is detailed as an application case study, achieving 100 Mbps+ throughput with an average consumption of 220 mW.

ML and near-ML MIMO detectors have attracted a lot of interest in recent years. However, almost all the reported implementations are delivered in ASICs or FPGAs. Our contribution is optimizing the near-ML MIMO detector for parallel programmable architectures, such as those with ILP and DLP features. In the proposed SSFE (selective spanning with fast enumeration), architecture-friendliness is explicitly introduced from the very beginning of the design flow. Importantly, high level algorithmic transformations make the dataflow pattern and structure fit architecture-characteristics very well. We enable abundant vector-parallelism with highly regular and deterministic dataflow in the SSFE; memory rearrangements, shuffling and non-predictable dynamism are all elaborately excluded. Hence, the SSFE can be easily parallelized and efficiently mapped onto ILP and DLP architectures. Furthermore, to fine-tune the SSFE on parallel architectures, extensive pre-compiler transformations are applied with the help of the application-level information. These optimize not only computation-operations but also address-generations and memory-accesses. Experiments show that the SSFE brings very efficient resource-utilizations on real-life VLIW architectures. Specifically, with the SSFE the percentage of NOPs instructions on VLIW is below 1%, even better than that achieved by the software-pipelined FFT. To the best of our knowledge, this is the first reported work about comprehensive optimizations of near-ML MIMO detectors for parallel programmable architectures.

The PFFT (Partial FFT) is an extended FFT where only part of input or output bins are used. By pruning the useless dataflow, the PFFT can potentially achieve a significant speedup in many important applications. Although theoretical aspects of the PFFT have been thoroughly studied in past three decades, efficient implementations were rarely reported. The most important obstacle is the highly irregular dataflow and the associated control flow. In addition, a size-N PFFT has 2Ndataflow possibilities, so that delivering both flexibility and efficiency in the same implementation is very challenging. This paper presents a generic scheme to map the highly irregular dataflow of arbitrary PFFT onto ILP architectures with highly efficient SWP (Software-Pipelining). Constraints and opportunities of algorithms and architecture are carefully analyzed and exploited. We introduce a multi-phase partitioning, bringing heterogeneous control structures and heterogeneous software pipelining schemes to minimize control overheads and to maximize the efficiency of SWP. The proposal has been tested with 10 representative benchmarks extracted from baseband applications. In experiments cycle-counts, instructions, NOPs, LID/LIP access/miss/hit are thoroughly analyzed. Comparing to full FFTs with efficient SWP, our work reduces 20.5% - 87.5% cycle-counts, 11.2% - 86.5% instructions, 16.1% - 79.4% LID cache accesses and 19.5% - 87.1% LIP cache accesses. To the best of our knowledge, this is the first reported work about the generic software-pipelined PFFT on ILP architectures.

User demand, standards and products for digital nomadic communications are evolving quickly. The combination of this changing environment together with the need for short time-to-market pushes for more flexible implementations. Software Defined Radios (SDR) have been introduced as the ultimate way to achieve such flexibility. The reduced energy budget required by battery-powered solutions makes the typical worst-case static dimensioning unaffordable under highly dynamic operating conditions. Instead, more energy-scalable algorithms and implementations are entailed to provide flexibility while maintaining the required energy efficiency. Particularly, energy-scalable implementations can exploit data format properties to offer different tradeoffs between accuracy and energy. In this paper, such a technique is developed and applied to the SDR implementation of a 2 antennas 200 Mbps+ OFDM (Orthogonal Frequency-Division Multiplexing) inner modem receiver on a C-programmable CGA (Coarse Grain Array) processor with extensive SIMD (Single Instruction Multiple Data) support. By defining separate implementations for different combinations of modulation scheme and coding rate, up to 3-fold gains can be achieved in the average energy consumption.

In this paper, we will present a near-ML (maximum likelihood) MIMO (multiple input multiple output) detector explicitly optimized for parallel programmable baseband architectures, such as DSPs (digital signal processors) with VLIW (very long instruction word), SIMD (single instruction multiple data) or vector processing features. First, we propose the SSFE (selective spanning with fast enumeration) algorithm as an architecture friendly near-ML MIMO detector. The SSFE has a distributed and greedy algorithmic structure that brings a completely deterministic and regular dataflow. This enables efficient parallelization on programmable architectures. More importantly, in order to exploit the abundant flexibility enabled by programmable architectures, we propose an efficient online algorithm to adaptively adjust the search range of the SSFE according to the numerical properties of MIMO channel matrixes. Such adaptiveness brings significant throughput improvements at negligible performance degradations. Specifically, on VLIW DSP TI TMS320C6416, such a dynamic adaptation brings 2.62 times to 28.6 times improvements (comparing to the static SSFE) for 1/2 turbo-coded 4 times 4 64 QAM transmissions over 3GPP suburban macro channels, delivering 80 - 103 Mbps average throughput.

The diversity and evolution of wireless communication standards are fast-pacing. This requires a wide-variety of baseband implementations within short time-to-market. Besides, always deeper submicron technology significantly increase design cost. This yields an increasing need for using reconfigurable or programmable solutions for an always larger part of wireless modems. Mapping the whole baseband functionality on a programmable architecture, as foreseen in tier-2 SDR, will become a must in future implementation. In handhelds where the multi-mode trend adds extra needs for programmability, the energy efficiency of SDR baseband is however a major concern. New processor architectures with major improvements on energy efficiency (GOPS/mW) are emerging but are still not sufficient to catch the continuously increasing complexity of wireless physical layers within the shrinking energy budget. To enable SDR in size, weight and power constrained devices, innovation is also needed at the software side. Specifically, a thorough architecture-aware algorithm implementation methodology is needed for the baseband signal processing functions, which account for most of the SDR computational complexity. We present the premise of such a methodology and illustrate its effectiveness on the design of key kernels from present and future wireless baseband systems.

ML and near-ML MIMO detectors have attracted a lot of interest in recent years. However, almost all of the reported implementations are delivered in ASIC or FPGA. Our contribution is to co-optimize the near-ML MIMO detector algorithm and implementation for parallel programmable base-band architectures, such as DSPs with VLIW, SIMD or vector processing features. Although for hardware the architecture can be tuned to fit algorithms, for programmable platforms the algorithm must be elaborately designed to fit the given architecture, so that efficient resource-utilizations can be achieved. By thoroughly analyzing and exploiting the interaction between algorithms and architectures, we propose the SSFE (selective spanning with fast enumeration) as an architecture-friendly near-ML MIMO detector. The SSFE has a distributed and greedy algorithmic structure that brings a completely deterministic and regular dataflow. The SSFE has been evaluated for coded OFDM transmissions over 802.11n channels and 3GPP channels. Under the same performance constraints, the complexity of the SSFE is significantly lower than the K-Best, the most popular detector implemented in hardware. More importantly, SSFE can be easily parallelized and efficiently mapped on programmable baseband architectures. With TI TMS320C6416, the SSFE delivers 37.4 - 125.3 Mbps throughput for 4x4 64 QAM transmissions. To the best of our knowledge, this is the first reported near-ML MIMO detector explicitly designed for parallel programmable architectures and demonstrated on a real-life platform.

Advances in low-power and low-cost sensor networks have led to solutions mature enough for use in a broad range of applications, requiring various degrees of reliability. To facilitate this, a broad range of options are possible to tune reliability, throughput or energy cost in the IEEE 802.15.4 standard defining the medium access control (MAC) and physical layer for sensor networks. Knowing how to tune those knobs however requires detailed models of the protocol behavior under different conditions. In our earlier work, we have proposed a very accurate model for the slotted Carrier Sense Multiple Access with Collision Avoidance (CSMA/CA) access scheme of the IEEE 802.15.4 standard for the unacknowledged transmission mode. Because of the design of the 802.15.4 carrier sensing mechanism, modeling the performance of the network in case of acknowledged transmissions is not a trivial extension. In this paper, we hence derive such model and illustrate through simulations that it is extremely accurate. Next, using the model, guidelines are derived to optimize the energy or throughput performance of sensor networks using the IEEE 802.15.4 standard.

Advances in low-power and low-cost sensor networks have led to solutions mature enough for use in a broad range of applications varying from health monitoring to building surveillance. The development of those applications has been stimulated by the finalization of the IEEE 802.15.4 standard, which defines the medium access control (MAC) and physical layer for sensor networks. One of the MAC schemes proposed is slotted carrier sense multiple access with collision avoidance (CSMA/CA), and this paper analyzes whether this scheme meets the design constraints of those low-power and low-cost sensor networks. The paper provides a detailed analytical evaluation of its performance in a star topology network, for uplink and acknowledged uplink traffic. Both saturated and unsaturated periodic traffic scenarios are considered. The form of the analysis is similar to that of Bianchi for IEEE 802.11 DCF only in the use of a per user Markov model to capture the state of each user at each moment in time. The key assumptions to enable this important simplification and the coupling of the per user Markov models are however different, as a result of the very different designs of the 802.15.4 and 802.11 carrier sensing mechanisms. The performance predicted by the analytical model is very close to that obtained by simulation. Throughput and energy consumption analysis is then performed by using the model for a range of scenarios. Some design guidelines are derived to set the 802.15.4 parameters as function of the network requirements.

In many portable devices, wireless network interfaces consume upwards of 30% of scarce system energy. Reducing the transceiver's power consumption to extend the system lifetime has therefore become a design goal. Our work is targeted at this goal and is based on the following two observations. First, conventional energy management approaches have focused independently on minimizing the fixed energy cost (by shutdown) and on scalable energy costs (by leveraging, for example, the modulation, code-rate and transmission power). These two energy management approaches present a tradeoff. For example, lower modulation rates and transmission power minimize the variable energy component, but this shortens the sleep duration thereby increasing fixed energy consumption. Second, in order to meet the quality of service (QoS) timeliness requirements for multiple users, we need to determine to what extent each system in the network may sleep and scale. Therefore, we propose a two-phase methodology that resolves the sleep-scaling tradeoff across the physical, communications and link layers at design time and schedules nodes at runtime with near optimal energy-efficient configurations in the solution space. As a result, we are able to achieve very low run-time overheads. Our methodology is applied to a case study on delivering a guaranteed QoS for multiple users with MPEG-4 video over a slow-fading channel. By exploiting runtime controllable parameters of actual RF components and a modified 802.11 medium access controller, system lifetime is increased by a factor of 3-to-10 in comparison with conventional techniques.

The improvement of spectral efficiency comes at the cost of exponential increment of signal processing complexity [1]. Hence, the energy-efficiency of baseband has recently turned out to be the bottleneck when deploying advanced air interfaces such as that in 4G. We advocate the scalable baseband design as a system level technique to aggressively optimize the average computation-load and associated energy-consumption. The key technique is to dynamically scale the baseband processing itself to the user requirement, the environment, the platform, etc. In this paper, we present the scalable design and VLIW processor based implementation of the OFDMA modulator, which is one of the most energy consuming parts of OFDMA and MIMO- OFDMA transmitters (in IEEE 802.16e , 3GPP LTE, etc.). Our work enables the OFDMA modulator to scale the modulation- accuracy and computation-load, so that the OFDMA modulator can dynamically reconfigure and work with minimal number of operations, whereas the required modulation-accuracy is still firmly guaranteed. Our work brings significant reductions in the average computation-load and associated energy-dissipation on real-life programmable platforms. Specifically, when the user is working with 16QAM and 1/2 coding rate (Turbo Coding) in a half-loaded 8-user system, the proposed scheme reduces 84% of the cycle-count and the associated energy-consumption on TI TMS320C6713, whereas the resulted Relative Constellation Error (RCE) is still lOdB better than the required RCE in IEEE 802.16e specifications.

Advanced adaptive filters have been shown to be very powerful for tracking time varying channels in various wireless communications system. However, the performance comes at the expense of highly resource-demanding implementations, especially in the context of programmable architecture based SDR. We present the optimizations for programmable implementation of QRD based SRI-RLS, which represents a large family of advanced adaptive filters. The key contribution of our work is to comprehensively and systematically remove the redundant operations in the QRD for SRI-RLS. Although most signal processing and scientific libraries implement householder reflection based QRD, we explore different alternatives and then choose given rotations based QRD to enable the aforementioned systematic redundancy removals. Our work significantly reduces the resource requirements (cycle count, energy consumption, etc.) of SRI-RLS implementation. Comparing to the widely accepted QRD implementation in numerical recipes, our work reduces 96.4% cycle-count on a typical baseband DSP (TI TMS320C6713), enabling efficient implementations. The paper shows that removing redundancy is very effective for modern statistical signal processing algorithms that largely rely on cascaded matrix operations.

In many portable devices, wireless network interfaces consume upwards of 30% of scarce system energy. Reducing the transceiver's power consumption to extend the system lifetime has therefore become a design goal. Our work is targeted at this goal and is based on the following two observations. First, conventional energy management approaches have focused independently on minimizing the fixed energy cost (by shutdown) and on scalable energy costs (by leveraging, for example, the modulation, code-rate and transmission power). These two energy management approaches present a tradeoff. For example, lower modulation rates and transmission power minimize the variable energy component, but this shortens the sleep duration thereby increasing fixed energy consumption. Second, in order to meet the quality of service (QoS) timeliness requirements for multiple users, we need to determine to what extent each system in the network may sleep and scale. Therefore, we propose a two-phase methodology that resolves the sleep-scaling tradeoff across the physical, communications and link layers at design time and schedules nodes at runtime with near optimal energy-efficient configurations in the solution space. As a result, we are able to achieve very low run-time overheads. Our methodology is applied to a case study on delivering a guaranteed QoS for multiple users with MPEG-4 video over a slow-fading channel. By exploiting runtime controllable parameters of actual RF components and a modified 802.11 medium access controller, system lifetime is increased by a factor of 3-to-10 in comparison with conventional techniques

Orthogonal Frequency Division Multiplexing (OFDM) is the modulation of choice for broadband wireless communications. Unfortunately, it comes at the cost of a very low energy efficiency of the analog transmitter. Numerous circuit-level and signal processing techniques have been proposed to improve that energy efficiency. However more disruptive improvement can be achieved at system-level, capitalizing on energy-scalable design and circuit reconfiguration to match the user requirements and operation environment. We describe the design of such an energy-scalable reconfigurable transmitter as well as its control strategy. Based on measurement carried out on the physical realization of this transmitter, the benefit of system-level energy management is shown. Energy-efficiency scalability ranges over 30%, which translates in an average system-level energy improvement of up to 40% compared to a non-scalable system.

Quality-Energy scalability has been proved to be an effective technique toward the cost reduction for signal processing. However, although it has large potentials for reducing signal processing energy in wireless transceivers, it has not yet been applied to them. In this paper, we elaborate an example and present a feedback control scheme to achieve Quality-Energy scalability for the chip level equalization in High Speed Downlink Packet Access (HSDPA) receivers. In conventional equalizers, the coefficients are updated according to the worst-case assumption that the channel is very dynamic. In our proposed approach, we take into account the speed of the channel variation to adapt the updating frequency. Specifically, a low-complexity closed-loop controller is designed to vary the update-interval while limiting the maximum equalization error. The proposed control scheme takes high order channel statistics implicitly into account without the need for an explicit estimator. Simulation results show that the Quality-Energy scalability for the equalizer results in significant energy reduction with minor quality degradation for channels with large coherence times. Specifically, for a pedestrian channel, 60% of the signal processing operations, and hence energy, can be saved with only 0.25 dBBERloss.

The IEEE 802.15.4 standard defines the medium access control (MAC) and physical layer for sensor networks. One of the MAC schemes proposed is slotted carrier sense multiple access with collision avoidance (CSMA/CA), and this paper analyzes whether this scheme meets the design constraints of low-power and low-cost sensor networks. The paper provides a detailed analytical evaluation of its performance in a star topology network for both saturated and unsaturated periodic traffic.The form of the analysis is similar to that of Bianchi for IEEE 802.11 DCF only in the use of a per user Markov model to capture the state of each user at each moment in time. The key assumptions to enable this important simplification and the coupling of the per user Markov models are however different, as a result of the very different designs of the 802.15.4 and 802.11 carrier sensing mechanisms. The performance predicted by the analytical model is very close to that obtained by simulation. Throughput and energy consumption analysis is then performed and design guidelines are derived.

During the last decade, wireless communication has seen a trend towards application diversification leading to a significant growth in users. With the availability of - however energy-limited - nomadic devices and real-time multimedia applications, user demand is shifting from simply asking for higher data rates to more complex requirements in terms of Quality of Service (QoS) and energy-efficiency. In this new context energy management is becoming a key success factor. Optimized energy-efficiency requires an energy management that continuously trades off QoS and energy adapting to varying user expectations and environment dynamics. But, QoS can only be evaluated on top of the whole protocol stack while energy consumption largely appears at the lower layers. To minimize overhead during the transitions between layers, we need to address the problem from a cross-layer perspective. We present a methodology that, based on systematic exploration, effective problem partitioning and minimal cross-layer interface, allows energy management in a cross-layer way, while maintaining efficient layered semantics. Different case studies in the context of wireless LAN (WLAN) for multimedia and data traffic transport are discussed, to show how cross-layer energy management can easily be included in systems running state-of-the-art protocols.

Wireless microsensor networks, which have been the topic of intensive research in recent years, are now emerging in industrial applications. An important milestone in this transition has been the release of the IEEE 802.15.4 standard that specifies interoperable wireless physical and medium access control layers targeted to sensor node radios. In this paper, we evaluate the potential of an 802.15.4 radio for use in an ultra low power sensor node operating in a dense network. Starting from measurements carried out on the off-the-shelf radio, effective radio activation and link adaptation policies are derived. It is shown that, in a typical sensor network scenario, the average power per node can be reduced down to 211 /spl mu/W. Next, the energy consumption breakdown between the different phases of a packet transmission is presented, indicating which part of the transceiver architecture can most effectively be optimized in order to further reduce the radio power, enabling self-powered wireless microsensor networks.

In many devices, wireless network interfaces consume upwards of 30% of scarce portable system energy. Extending the system lifetime by minimizing communication power consumption has therefore become a priority. Conventional energy management techniques focus independently on minimizing the fixed energy consumption of the transceiver circuit or on scalable transmission control. Fixed energy consumption is reduced by maximizing the transceiver shutdown interval. In contrast, variable transmission rate, coding and power can be leveraged to minimize energy costs. These two energy management approaches present a tradeoff in minimizing the overall system energy. For example, variable energy costs are minimized by transmitting at a lower modulation rate and transmission power, but this also shortens the sleep duration thereby increasing fixed energy consumption. We present a methodology for energy-efficient resource allocation across the physical layer, communications layer and link layer. Our methodology is aimed at providing QoS for multiple users with bursty MPEG-4 video over a time-varying channel. We evaluate our scheme by exploiting control knobs of actual RF components over a modified IEEE 802.11 MAC. Our results indicate that the system lifetime is increased by a factor of 2 to 5 compared to the gains of conventional techniques.

Turbo codes have become an attractive forward error correction scheme for broadband communications, providing near optimal coding gain. However, the limited throughput, the large latency and the significant power consumption of their current implementations make them hardly suitable for future broadband communication systems (up to 1 Gbit/s). We have developed an innovative turbo-decoding architecture that overcomes these major drawbacks. We increased drastically the throughput and decreased the latency by introducing a high level of parallelism. We reduced significantly the power consumption by optimizing the memory architecture and organization. This paper presents the proposed architecture as a generic, scalable and parametrizable entity. Design trade-offs regarding decoding performance, energy consumption and silicon area are extensively explored and summarized in cost versus throughput curves, enabling an optimal tuning of the proposed architecture to future applications. A net coding gain of 8 dB, a throughput of 500 Mbit/s and a latency of 10 /spl mu/s are achievable with a typical power budget of 1 W and a die size of 20 mm/sup 2/ in 0.18 /spl mu/m CMOS technology. At lower throughput (around 10 Mb/s), the power can be reduced to 10 mW and the area to 5 mm/sup 2/.