With the onset of the COVID-19 pandemic, colleges and universities had to switch abruptly to remote teaching. This paper describes our experiences teaching an undergraduate Embedded Systems course in a synchronous-remote format to students spread across the globe. Lectures were delivered via Zoom with recordings provided as backup for students who missed lectures. For the laboratory, low-cost lab kits were assembled and shipped to each student consisting of a microcontroller development board, and LCD display, a breadboard, and a collection of electronic parts. Students worked in lab each week in Zoom breakout rooms with the instructor available to answer questions and help troubleshoot problems. The course culminated with a project defined by each student group and constructed from the parts kit and, in some cases, a few additional parts that were purchased separately. Despite the inevitable difficulties of remote instruction, students developed interesting projects and reported a positive learning experience overall.

Caches can be one of the more difficult subjects to teach in computer organization introductory courses. To aid this, we introduce an applet, VCache, which can visualize cache interactions on various caches with different sizes, structures and policies. The visualization is achieved by animating and color-highlighting the activity and showing the contents of the cache. Using this, students can learn the principles of the cache and the performance implications, by experimenting different sets of memory accesses on different caches.

This paper describes an FPGA-based accelerator for maze routing applications such as integrated circuit detailed routing. The accelerator efficiently supports multiple layers, multi-terminal nets, and rip up and reroute. By time-multiplexing multiple layers over a two-dimensional array of processing elements, this approach can support multi-layer grids large enough for detailed routing while providing at 1-2 orders of magnitude speedup over software running on a modern desktop computer. The current implementation supports a 32 × 32 routing grid with up to 16 layers in a single Xilinx XC2V6000 FPGA. Up to 64 × 64 routing grids are feasible in larger commercially available FPGAs. Performance measurements (including interface overhead) show a speedup of 29X-93X over the classic Lee Algorithm and 5X-19X over the A* Algorithm. An improved interface design could yield significantly larger speedups.

This paper describes a new design for a hardware accelerator to support grid-based Maze Routing. Based on the direct mapped approach of Breuer and Shamsa [3], this work refines their design to substantially reduce the hardware requirements of each processing element while at the same time adding support for mulitilayer routing and fast iterative routing. An RTL implementation has been developed for this design in VHDL, and initial results show promise for its realization using ASIC, custom, or FPGA technology.

An approach to scheduling in high-level synthesis that meets timing constraints while attempting to minimize hardware resource costs is described. The approach is based on a modified control/data-flow graph (CDFG) representation called SALSA. SALSA provides a simple move set that allows alternative schedules to be quickly explored while maintaining timing constraints. It is shown that this move set is complete in that any legal schedule can be reached using some sequence of move applications. In addition, SALSA provides support for scheduling with conditionals, loops, and subroutines. Scheduling with SALSA is performed in two steps. First, an initial schedule that meets timing constraints is generated using a constraint solution algorithm adapted from layout compaction. Second, the schedule is improved using the SALSA move set under control of a simulated annealing algorithm. Results show the scheduler's ability to find good schedules which meet timing constraints in reasonable execution times.>

A new visual approach to creating and manipulating symbolic descriptions of VLSI microarchitectures at the register-transfer (RT) level is described. The MIES visual RT description provides a number of views of a microarchitecture's datapath and controller that visually emphasize different aspects of a design. The key view ties together a symbolic description of the RT operations invoked by a controller with the flow and manipulation of data in the datapath. A prototype implementation demonstrates a number of interesting capabilities, which are illustrated using several examples.>

First, an initial schedule that satisfies all timing constraints is generated using algorithms adapted from layout compaction. This schedule is then improved with respect to resource usage using simulated annealing. SALSA provides for efficient exploration of alternative schedules while supporting timing constraints, conditionals, loops, and subroutines. The SALSA scheduling procedure is described in detail. An implementation of the approach shows promising results.>

This paper describes the definition and implementation of a multilevel representation which includes both behavioral and structural information. Information for the representation is generated by the CMU-DA synthesis system. A timing abstraction aid which extracts logic level timing information from a detailed implementation and makes it available for the ISPS behavioral simulator is discussed. Such a multilevel representation and design aid allows the system level designers to be in a closed loop of design aids with the technology level designers.

A design representation that incorporates descriptions at more than one level of abstraction is called a multilevel representation. This paper describes a multilevel representation which includes behavioral and structural levels of description, and a multilevel analysis aid, called timing abstraction, which extracts timing information from a structural design and adds it to a behavior level description. With this design aid, alternate implementations of the same behavior, generated using the CMU-DA synthesis software, can be compared using a behavior level simulator. The timing accuracy is that of the microcode impleinentation, while the speed of the simulation is that of a behavior level simulator.