After almost a decade of research, development of more efficient imprecise computational blocks is still a major concern in imprecise computing domain. There are many instances of the introduced imprecise components of different types, while their main difference is that they propose different precision-cost-performance trade-offs. In this paper, a novel comprehensive model for the imprecise components is introduced, which can be exploited to cover a wide range of precision-cost-performance trade-offs, for different types of imprecise components. The model helps to find the suitable imprecise component based on any desired error criterion. Therefore, the most significant advantage of the proposed model is that it can be simply exploited for design space exploration of different imprecise components to extract the suitable components, with the desired precision-cost-performance trade-off for any specific application. To demonstrate the efficiency of the proposed model, two novel families of Lowest-cost Imprecise Adders (LIAs) and Lowest-cost Imprecise Multipliers (LIMs) are introduced in the paper, which are systematically extracted based on exploration of the design space provided by the proposed model. A wide range of simulation and synthesis results are also presented in the paper to prove the comparable efficiency of the systematically extracted LIA/LIM structures with respect to the most efficient existing human-made imprecise components both individually and in a Multiply-Accumulate application.

Due to considerable effectiveness of the imprecise computing paradigm in hardware implementation of many applications, great attention has been recently paid by many research groups to develop different novel imprecise computational blocks such as adders and multipliers. Traditionally, the imprecise blocks are developed in an application independent manner, just similar to development of a conventional precise block. This article investigates the systematic application oriented development of the imprecise computational blocks which results in more customized components. The main focus is on the development of customized imprecise adder/multiplier for efficient implementation of a general multiply-accumulate (MAC) block as the basic building block of many imprecision tolerant applications including digital signal processing and soft computing. To develop some customized blocks for the MAC, the error behaviors of the suitable imprecise adder and multiplier are first extracted by analyzing the MAC. Based on analysis results, efficient small constant mean-error imprecise adder and multiplier are developed based on a systematic mathematical-logical approach. A wide range of synthesis and simulation results are provided to demonstrate efficiency of custom developed imprecise blocks with respect to some of the best existing imprecise blocks in a general MAC and a real 2D-Convolution application.

Reliability should be identified as the most important challenge in future nano-scale very large scale integration (VLSI) implementation technologies for the development of complex integrated systems. Normally, fault tolerance (FT) in a conventional system is achieved by increasing its redundancy, which also implies higher implementation costs and lower performance that sometimes makes it even infeasible. In contrast to custom approaches, a new class of applications is categorized in this paper, which is inherently capable of absorbing some degrees of vulnerability and providing FT based on their natural properties. Neural networks are good indicators of imprecision-tolerant applications. We have also proposed a new class of FT techniques called relaxed fault-tolerant (RFT) techniques which are developed for VLSI implementation of imprecision-tolerant applications. The main advantage of RFT techniques with respect to traditional FT solutions is that they exploit inherent FT of different applications to reduce their implementation costs while improving their performance. To show the applicability as well as the efficiency of the RFT method, the experimental results for implementation of a face-recognition computationally intensive neural network and its corresponding RFT realization are presented in this paper. The results demonstrate promising higher performance of artificial neural network VLSI solutions for complex applications in faulty nano-scale implementation environments.

This paper discusses software implementation issues of different defuzzification procedures in fuzzy systems. Three new defuzzification methods are introduced which are suitable for efficient software and also hardware implementations. A set of seven important existing defuzzification methods are reviewed and compared with these new methods for different software implementation approaches. The C models of all methods are prepared to perform a comprehensive analysis on the output accuracy of different methods. The results prove the superiority of our new proposed methods. In another study, three categories of low-level assembly models are developed for each method to evaluate its software execution time and instruction count when executed on each of three chosen popular processors. Namely, Texas Instruments C6xcopy DSP, Intel's Pentiumcopy IV, and IBM's PowerPC PPC405copy processors are used as the running engines for this comparison. Some accuracy-speed analysis diagrams are then introduced to guide the designers for choosing the defuzzification method which best suites their application requirements.

This paper deals with hardware implementation aspects of the defuzzification block in fuzzy controllers and processors. Three new defuzzification methods are introduced which are suitable for low cost hardware implementation. A complete set of common existing defuzzification methods are reviewed to be compared with these new methods from different hardware implementation aspects. Two different hardware models with different structures are developed for each method. The first model realizes the full combinational or fastest possible hardware implementation, and the second model demonstrates the full sequential or the smallest possible hardware implementation of each method. All models are synthesized on 0.18 micron CMOS technology cells to analyze and compare the area, delay and power consumption of different realizations of defuzzification methods. Some area-power-delay-accuracy analysis diagrams are then introduced according to the synthesis results to guide the designers through choosing the defuzzification method and also the implementation structure which best suites their application from implementation cost, speed, power consumption and output accuracy points of view