Summary form only given, as follows. We investigate the use of nanoelectronic structures in cellular neural network (CNN) architectures, for future high-density and low-power CMOS-nanodevice hybrid circuits. We present simulation results for Single Electron Tunneling (SET) transistors configured as a voltage-to-current transducer for CNN cells. We also present an example of quantum-dot cellular arrays which may be used to realize binary CNN algorithms. Nanoelectronics offers the promise of ultra-low power and ultra-high integration density. Several device structures have been proposed and realized experimentally, yet the main challenge remains the organization of these devices in new circuit architectures. Here, we investigate the use of nanodevices in CNN architectures. Specifically, we focus on nanostructures based on SET devices and Coulomb-coupled quantum-dot arrays, the so-called Quantum-Dot Cellular Automata (QCA). CNN-type architectures for nanostructures are motivated by the following considerations: on the one hand, locally-interconnected architectures appear to be natural for nanodevices where some of the connectivity may be provided by direct physical device-device interactions. On the other hand, CNN arrays with sizes on the order of 1000-by-1000 (which are desirable for applications such as image processing) will require the use of nanostructures since such integration densities are beyond what can be achieved by scaling conventional CMOS devices.

A novel technique has been developed for the fabrication of Si quantum dot structures with controllable electron number through both top and side gates. We have tested devices ranging in size from 40 to 200 nm. By varying the density with the top gate, and controlling the input and output barriers of the dot with the side gates, conductance peaks are observed which map details of the energy level within the dot as well as the interaction of the electrons with one another.

We present PMC-3D, a parallel three-dimensional (3-D) Monte Carlo device simulator for multiprocessors. The parallel algorithm is an extension of the standard Monte Carlo device simulation model in 3-D, in which the particle dynamics generated from the stochastic Monte Carlo method are solved simultaneously with Poisson's equation on a 3-D mesh using finite differences. Due to the large computational requirements of 3-D device simulation, it is necessary to parallelize both the Poisson solver and the Monte Carlo simulation phase of the device simulator. The parallel algorithms were implemented on a 1024-node distributed memory nCUBE multicomputer and a 4-mode shared memory Ardent multiprocessor. We validate the accuracy of our implementations by generating the static characteristics of a MESFET and present test results on the fixed and scaled speedups obtained on the two types of parallel computers. Improvements in performance are observed utilizing dynamic load balancing for the distributed memory case.>