In the original correspondence,1 Cantarella assumed a system consisting ot n parallel identical elements, each with a constant failure rate A. The system is repaired every T hours. An approximation n(n -1) A2T/2 for the average failure rate was derived. In further correspondence, 2 Nilsson derived an exact ciosed form expression for the failure rate. In this comment, we correct an algebraic error in Nilsson's approximation for small values of A. T, and also point out the relevance of both correspondences to the case where n is small, as in a triple modular redundant (TMR) system.

A memory organization is considered for which a large number of faults can be tolerated at a low cost in redundancy. The primitive element in the memory is a large-scale integrated (LSI) chip that realizes a section of memory, b bits wide by y words long, together with an address decoder for the y words. The chips (including spares) are connected via a switching network so that the memory can be reconfigured effectively in the presence of chip failures. The main results of the paper relating to the switching network are as follows.

“Non-Analytical Iterative Processes” include those often termed “Digit-by-digit methods” or “doubling and halving methods.” This paper develops methods whereby such processes may be constructed for the calculation of a variety of mathematical functions.