In this paper, we propose a novel multi-mode/multi-corner sparse regression (MSR) algorithm to build large-scale performance models of integrated circuits at multiple working modes and environmental corners. Our goal is to efficiently extract multiple performance models to cover different modes/corners with a small number of simulation samples. To this end, an efficient Bayesian inference with shared prior distribution (i.e., model template) is developed to explore the strong performance correlation among different modes/corners in order to achieve high modeling accuracy with low computational cost. Several industrial circuit examples demonstrate that the proposed MSR achieves up to 185 × speedup over least-squares regression [14] and 6.7 × speedup over least-angle regression [7] without surrendering any accuracy.

While statistical analysis has been considered as an important tool for nanoscale integrated circuit design, many IC designers would like to know the design-specific worst-case corners for circuit debugging and failure diagnosis. In this paper, we propose a novel algorithm to efficiently extract the worst-case corners for nanoscale ICs. Our proposed approach mathematically formulates a quadratically constrained quadratic programming (QCQP) problem for corner extraction. Next, it applies the Lagrange duality theory to convert the non-convex QCQP problem to a convex semi-definite programming (SDP) problem that is easier to solve. Our circuit example designed in a commercial CMOS process demonstrates that the proposed SDP formulation can find the worst-case corners both efficiently and robustly, while the traditional QCQP fails to achieve global convergence.

This paper proposes a general hierarchical analysis methodology, HiPRIME, to efficiently analyze RLKC power delivery systems. After partitioning the circuits into blocks, we develop and apply the IEKS (Improved Extended Krylov Subspace) method to build the multiport Norton equivalent circuits which transform all the internal sources to Norton current sources at ports. Since there are no active elements inside the Norton circuits, passive or realizable model order reduction techniques such as PRIMA can be applied. The significant speed improvement, 700 times faster than Spice with less than 0.2% error and 7 times faster than a state-of-the-art solver, InductWise, is observed. To further reduce the top-level hierarchy runtime, we develop a second-level model reduction algorithm and prove its passivity.

To ensure the power and signal integrity of modern VLSI circuits, it is crucial to analyze huge amount of nonlinear devices together with enormous interconnect and even substrate parasitics to achieve the required accuracy. Neither traditional circuit simulation engines such as SPICE nor switch-level timing analysis algorithms are equipped to handle such a tremendous challenge in both efficiency and accuracy. We establish a solid framework that simultaneously takes advantage of a hierarchical nonlinear circuit simulation algorithm and an advanced large-scale linear circuit simulation method using a new predictor-corrector algorithm. Under solid convergence and stability guarantees, our simulator, HiSIM, a hierarchical interconnect-centric circuit simulator, is capable of handling the post-layout RLKC power and signal integrity analysis task efficiently and accurately. Experimental results demonstrate over 180X speed up over the conventional flat simulation method with SPICE-level accuracy.

Clock distribution is crucial for timing and design convergence in high-performance very large scale integration designs. Minimum-delay/power zero skew buffer insertion/sizing and wire-sizing problems have long been considered intractable. In this paper, we present ClockTune , a simultaneous buffer insertion/sizing and wire-sizing algorithm which guarantees zero skew and minimizes delay and power in polynomial time. Extensive experimental results show that our algorithm executes very efficiently. For example, ClockTune achieves 45/spl times/ delay improvement for buffering and sizing an industrial clock tree with 3101 sink nodes on a 1.2-GHz Pentium IV PC in 16 min, compared with the initial routing. Our algorithm can also be used to achieve useful clock skew to facilitate timing convergence and to incrementally adjust the clock tree for design convergence and explore delay-power tradeoffs during design cycles. ClockTune is available on the web (http://vlsi.ece.wisc.edu/Tools.htm).

In 21st-Century VLSI design, clocking plays crucial roles for both performance and timing convergence. Due to their non-convex nature, optimal minimum-delay/area zero-skew wire-sizing problems have long been considered intractable. None of the existing approaches can guarantee optimality for general clock trees to the authors' best knowledge. In this paper, we present an ε-optimal zero-skew wire-sizing algorithm, ClockTune, which guarantees zero-skew with delay and area within ε distance to the optimal solutions in pseudo-polynomial time. Extensive experimental results show that our algorithm executes very efficiently in both runtime and memory usage. For example, ClockTune takes less than two minutes and 35MB memory to size an industrial clock tree with 3101 sink nodes within 2% to the optimal solution on a 533MHz Pentium III PC. Our algorithm can also be used to achieve useful clock skew to facilitate timing convergence and to incrementally adjust clock tree for design convergence and explore delay/power tradeoffs during design cycles. ClockTune is available on the web [13].

A robust, efficient, and accurate inductance extraction and simulation tool, INDUCTWISE, is developed and described in this paper. This work advances the state-of-the-art inductance extraction and simulation techniques, and has several major contributions. First, albeit the great benefits of efficiency, the recently proposed inductance matrix sparsification algorithm, the-method (Ji et al. 2001), has a flaw in the stability proof for general geometry. We provide a theoretical analysis as well as a provable stable algorithm for it. Second, a robust window-selection algorithm is presented for general geometry. Third, integrated with the nodal analysis formulation, INDUCTWISE achieves exceptional performance without frequency-dependent complex operations and directly gives time-domain responses. Experimental results show that INDUCTWISE extractor and simulator have dramatic speedup compared to FastHenry and SPICE3, respectively. It has been well tested and released on the web for public usage (Available: http://vlsi.ece.wisc.edu/Inductwise.htm).

This paper proposes a general hierarchical analysis methodology, HiPRIME, to efficiently analyze RLKC power delivery systems. After partitioning the circuits into blocks, we develop and apply the IEKS (Improved Extended Krylov Subspace) method to build the Multi-port Norton Equivalent circuits which transform all the internal sources to Norton current sources at ports. Since there is no active elements inside the Norton circuits, passive or realizable model order reduction techniques such as PRIMA can be applied. To further reduce the top-level hierarchy runtime, we develop a second-level model reduction algorithm and prove its passivity. Experimental results show 400-700X runtime improvement with less than 0.2% error.

We develop a robust, efficient, and accurate tool, which integrates inductance extraction and simulation, called INDUCTWISE. This paper advances the state-of-the-art inductance extraction and simulation techniques and contains two major parts. In the first part, INDUCTWISE extractor, we discover the recently proposed inductance matrix sparsification algorithm, the K-method[1], albeit its great benefits of efficiency, has a major flaw on the stability. We provide both a counter example and a remedy for it. A window section algorithm is also presented to preserve the accuracy of the sparsification method. The second part, INDUCTWISE simulator, demonstrates great efficiency of integrating the nodal analysis formulation with the improved K-method. Experimental results show that INDUCTWISE has over 250x speedup compared to SPICE3. The proposed sparsification algorithm accelerates the simulator another 175x and speeds up the extractor 23.4x within 0.1% of error. INDUCTWISE can extract and simulate an 118K-conductor RKC circuit within 18 minutes. It has been well tested and released on the web for public usage. (http://vlsi.ece.wisc.edu/Inductwise.htm)

In this paper, we propose preconditioned Krylov-subspace iterative methods to perform efficient DC and transient simulations for large-scale linear circuits with an emphasis on power delivery circuits. We also prove that a circuit with inductors can be simplified from MNA to NA format, and the matrix becomes an s.p.d matrix. This property makes it suitable for the conjugate gradient with incomplete Cholesky decomposition as the preconditioner, which is faster than other direct and iterative methods. Extensive experimental results on large-scale industrial power grid circuits show that our method is over 200 times faster for DC analysis and around 10 times faster for transient simulation compared to SPICE3. Furthermore, our algorithm reduces over 75% of memory usage than SPICE3 while the accuracy is not compromised.