Storing data structures in high-capacity byte-addressable persistent memory instead of DRAM or a storage device offers the opportunity to (1) reduce cost and power consumption compared with DRAM, (2) decrease the latency and CPU resources needed for an I/O operation compared with storage, and (3) allow for fast recovery as the data structure remains in memory after a machine failure. The first commercial offering in this space is Intel® Optane™ Direct Connect (Optane™ DC) Persistent Memory. Optane™ DC promises access time within a constant factor of DRAM, with larger capacity, lower energy consumption, and persistence. We present an experimental evaluation of persistent transactional memory performance, and explore how Optane™ DC durability domains affect the overall results. Given that neither of the two available durability domains can deliver performance competitive with DRAM, we introduce and emulate a new durability domain, called PDRAM, in which the memory controller tracks enough information (and has enough reserve power) to make DRAM behave like a persistent cache of Optane™ DC memory.In this paper we compare the performance of these durability domains on several configurations of five persistent transactional memory applications. We find a large throughput difference, which emphasizes the importance of choosing the best durability domain for each application and system. At the same time, our results confirm that recently published persistent transactional memory algorithms are able to scale, and that recent optimizations for these algorithms lead to strong performance, with speedups as high as 6× at 16 threads.

In this paper, we introduce Insistent Spectrum Sensing Data Falsification (ISSDF) as a new practical and destructive attack model aimed at distributed cooperative spectrum sensing schemes that are based on iterative average consensus. We compare various linear iteration-based and iterative gossip-based schemes in terms of primary user detection performance and convergence speed under this attack. Moreover, we devise a trust management scheme to mitigate the attack and we propose a practical trust-aware consensus-based scheme for distributed cooperative spectrum sensing which is resilient to ISSDF. Finally, we quantify the performance improvement due to trust management through extensive simulations.

High throughput parallel interleaver design is a major challenge in designing parallel turbo decoders that conform to high data rate requirements of advanced standards such as HSPA+. The hardware complexity of the HSPA+ interleaver makes it difficult to scale to high degrees of parallelism. We propose a novel algorithm and architecture for on-the-fly parallel interleaved address generation in UMTS/HSPA+ standard that is highly scalable. Our proposed algorithm generates an interleaved memory address from an original input address without building the complete interleaving pattern or storing it; the generated interleaved address can be used directly for interleaved writing to memory blocks. We use an extended Euclidean algorithm for modular multiplicative inversion as a step towards reversed intra-row permutations in UMTS/HSPA+ standard. As a result, we can determine interleaved addresses from original addresses. We also propose an efficient and scalable hardware architecture for our method. Our design generates 32 interleaved addresses in one cycle and satisfies the data rate requirement of 672 Mbps in HSPA+ while the silicon area and frequency is improved compared to recent related works.

Parallel architecture is required for high throughput turbo decoder to meet the data rate requirements of the emerging wireless communication systems. However, due to the severe memory conflict problem caused by parallel architectures, the interleaver design has become a major challenge that limits the achievable throughput. Moreover, the high complexity of the interleaver algorithm makes the parallel interleaving address generation hardware very difficult to implement. In this paper, we propose a parallel interleaver architecture that can generate multiple interleaving addresses on-the-fly. We devised a novel scheduling scheme with which we can use more efficient buffer structures to eliminate memory contention. The synthesis results show that the proposed architecture with the new scheduling scheme can significantly reduce memory usage and hardware complexity. The proposed architecture also shows great flexibility and scalability compared to prior work.

The high processing complexity of data detection in the large-scale multiple-input multiple-output (MIMO) uplink necessitates high-throughput VLSI implementations. In this paper, we propose - to the best of our knowledge - first matrix inversion implementation suitable for data detection in systems having hundreds of antennas at the base station (BS). The underlying idea is to carry out an approximate matrix inversion using a small number of Neumann-series terms, which allows one to achieve near-optimal performance at low complexity. We propose a novel VLSI architecture to efficiently compute the approximate inverse using a systolic array and show reference FPGA implementation results for various system configurations. For a system where 128 BS antennas receive data from 8 single-antenna users, a single instance of our design processes 1.9M matrices/s on a Xilinx Virtex-7 FPGA, while using only 3.9% of the available slices and 3.6% of the available DSP48 units.

To comply with the evolving wireless standards, base stations must provide greater data rates over the serial data link between base station processor and RF unit. This link is especially important in distributed antenna systems and cooperating base stations settings. This paper explores the compression of baseband signal samples prior to transfer over the above-mentioned link. We study lossy and lossless compression of baseband signals and analyze the cost and gain of each approach. Sample quantizing is proposed as a lossy compression scheme and it is shown to be effective by experiments. With QPSK modulation, sample quantizing achieves a compression ratio of 4:1 and 3.5:1 in downlink and uplink, respectively. The corresponding compression ratios are 2.3:1 and 2:1 for 16-QAM. In addition, lossless compression algorithms including arithmetic coding, Elias-gamma coding, and unused significant bit removal, and also a recently proposed baseband signal compression scheme are evaluated. The best compression ratio achieved for lossless compression is 1.5:1 in downlink. Our simulations and over-the-air experiments suggest that compression of baseband signal samples is a feasible and promising solution for increasing the effective bit rates of the link to/from remote RF units without requiring much complexity and cost to the base station.

Key-based interval splitting arithmetic coding (KSAC) has been proposed to improve the security of traditional arithmetic coding (AC). Chosen-plaintext attacks have been proposed for KSAC when the same key is used to encrypt different messages. In this paper, we consider a stronger version of KSAC, where different keys are used to encrypt different messages. We then use message indistinguishability to prove that this version of KSAC is insecure under ciphertext-only attacks, a weaker form of attack than chosen-plaintext attacks. Indistinguishability in the presence of an eavesdropper is a security definition equivalent to semantic security. We prove the insecurity over the alphabet {A,B} withpB=(1/2(1+2s)) andpA=1-pBwherepAandpBare the probabilities of the source generating A and B, respectively, andsis the number of bits in each splitting key.

Modifications of arithmetic coding (AC) have been proposed to improve the security of traditional AC. Two main modifications to AC are randomized AC (RAC) and AC with key-based interval splitting (KSAC). Chosen-plaintext attacks have been proposed for these two methods when the same key is used to encrypt different messages. We first give a definition for security of encryption using AC that is based on the inability of the adversary to distinguish between the encryption of one plaintext from the encryption of another. Using this definition, we prove that RAC is insecure even if a new random key is used to compress every message. Our proof assumes that the adversary can only eavesdrop on the ciphertext and cannot request encryptions of chosen-plaintexts. We then prove that the method of first-compress-then-encrypt, where the encryption is performed by a bitwise xor of the compressed output with a pseudorandom bit sequence, is provably secure with respect to chosen-plaintext attacks. If the pseudorandom bit sequence is derived in advance using Advanced Encryption Standard (AES) in the counter mode, then the first-compress-then-encrypt method results in a performance penalty of only a few two input xor-gate delays.

In this paper we consider authentication of multiple messages m1, m2, …., mLwhere each message mi consists of s bits. We propose a scheme for the computation of a message authentication code (MAC) tag t, of m1, m2, …., mLthat takes constant time (time that is independent of L) and has a tag length that is constant or independent of L. The verification time of the proposed scheme is also constant. Current schemes result in tag computation and verification times proportional to L and are hence less efficient than the proposed scheme. The proposed scheme uses a modification of division by an irreducible polynomial over GF(2) in order to compress the L messages. The compressed result is then input to a pseudorandom function Fk(.) to obtain a secure tag t. We prove the security of the proposed MAC scheme. The proposed scheme has applications in sensor networks where many messages having one tag can reduce the number of bits being transmitted by a sensor node, thereby reducing the power consumption at a sensor node. Another application is in multimedia authentication, where a large multimedia data file can be split up into smaller segments whose MAC tag can be computed at high speed using the proposed scheme.