A representation of a Boolean function is canonical if, given a variable order, only one instance of the representation is possible for the function. A computation is canonical if the result depends only on the Boolean function and a variable order, and does not depend on how the function is represented and how the computation is implemented.

While physical design continues to fight the traditional data capacity and runtime challenges, it has also become critically important to overcome many drawbacks of the silicon technology roadmap.

Crossroads have always been challenging: they require a decision; in Egyptian and Greek mythology they were often guarded by two sphinxes trying to cheat the traveler with their riddles. The two sphinxes, the knight and the knave, the lady and the tiger, are just few instances of difficult puzzles that have kept logicians and mathematicians busy for the last 5,000 years. Today, you are walking down Moore's Law road when you come to a crossroads: one road brings you into the land of emerging technologies: 14, 10 and 7 nanometer, FDSOI, FinFET, 3D-IC,… beyond and below; the other road holds you into the land of established technologies: 28, 40, 65, and 90 nanometers, possibly even above, A&M/S, MEMS,… Choosing the right road is critical to lead your project and your company to success, but making the right decision is increasingly difficult, as it encompasses complex technical and economic considerations. However, unlike the mythological traveler, you won't run into the sphinxes but, rather, into some of our industry best experts; unlike the sphinxes, they will strive to provide you with honest advice about the “road conditions”, and you are allowed to ask multiple questions to them to figure out which road is the best for you.

Over the last decade, the semiconductor industry has advanced CMOS technology from 90 to 22/20 nanometers, and the EDA industry has developed a great deal of tools, methodologies, and flows to help “gigascale” design, implementation and verification, at these “leading edge” technology nodes. However, in 2010 approximately 75% of design starts used 130 nanometers or greater CMOS technologies [1], and 25% of wafers were fabricated using these “trailing edge” technologies [2]. There are possibly more designers working at 130 nanometers and above than at 90 nanometers and below, and there is certainly much more to electronics than just digital CMOS and microprocessors, and in order for the electronic industry to continue delivering on promises, “More than Moore” is needed, besides “More of Moore”. What is EDA doing - or what should EDA do - in order to help design implementation and verification at trailing edge technologies?

With the increasing interplay between physical design and manufacturing, the next five years will present major challenges for the semiconductor industry. EDA tools must evolve substantially to tackle the demands of increasingly complex designs, power constraints, and manufacturing yield. In his address, Dr. Antun Domic, senior vice president and general manager of the Implementation Group at Synopsys, will present his thoughts on the future of design and its role in enabling the semiconductor roadmap to continue at the current pace

Everybody agrees that curing DFM/DFY issues is of paramount importance at 65 nanometers and beyond. Unfortunately, there is disagreement about how and when to cure them. "Surgeons" suggest a GDSII-centered approach, potentially invasive, while "family doctors" recommend a more pervasive approach, starting from RTL. As in real life, "surgery" and "medicine" represent two different schools of thought in the DFM/DFY arena. Both involve risks. This panel examine these two approaches from high-level design all the way to manufacturing. We have assembled a set of panelists that represent a broad cross-section of semiconductor industry. Although there is general agreement among the panelists that both approaches are necessary and that prevention is the best way to proceed, they also acknowledge that the surgery may be unavoidable in such "hazardous" conditions as state-of-the-art technologies. However, as always, "the devil is in the details", and the diverse approaches to DFM presented below should make this panel quite interesting. We are also counting on the feedback from the IC design community to assess if these approaches are sufficient and practical enough to deal with the "health hazards". We are looking forward to an exciting discussion that will challenge our esteemed panelists

While transistors per square millimeter and on-chip clock keep scaling smoothly according to Moore’s Law, Vdd does not, nor does Vth. This leads to a dramatic increase in chip power density, and to a significant shift in the balance between dynamic and leakage power. In spite of the recent effort made by EDA vendors in delivering novel solutions that help mitigating the effects on power consumption of technology scaling, the question of whether EDA industry is taking the low-power matter seriously still remains. This session will provide an answer to this intriguing question, by first offering a short review of the state of-the-art in design technologies for dynamic and leakage power minimisation. The session will then continue with a public “trial”, in which OEMs, IDMs, IP and fabless semiconductor vendors will play the role of the public prosecutor, against defendant EDA industry. The court’s ruling will tell us about the future targets the EDA vendors will pursue in low-power design technologies.

Overview Two years ago, DAC-2001 attendees enjoyed a thrilling debatepanel, “Who’s Got Nanometer Design Under Control?”, pitting sky-is-falling Physics die-hards against not-to-worry Methodology gurus. Then, the DAC audience overwhelmingly voted the match for the Methodologists. Now, we've just gone through the biggest business downturn in the industry's history, and we're hearing more and more about chip failures due to 130nm physical effects. Both physics and economics are a lot worse than we thought two years ago. Where are those simple, correct-by-construction methodologies for signal integrity, power integrity, low-power, etc. that we were promised? Were we bamboozled by glib promises from those Methodologists? In this session, we bring back the panelists from two years ago, not for another debate, but to hear well-reasoned perspectives on how to prioritize spending to address nanometer design challenges. Yes, methodology can solve any problem – but now we want to know which problems, in what priority order, at what cost. The panel will address the following questions. • What are the economic impacts and significance of the key nanometer design challenges, relative to each other? • Which nanometer design problems merit responsible R&D investment, in what amounts and proportion? • What is the likelihood of success, both near-term and longterm, in solving key nanometer design challenges? • Where will the answers come from? To keep the discussion very concrete, each panelist will be given a $100 budget, and must defend their allocation of this budget to attack various design problems. Where should the $100 be spent? The audience will determine the best-reasoned allocation, and the winning panelist keeps all the money.

This special panel session brings together several leading technologists to discuss the challenges and solutions in constructing SoC designs that achieve their performance goals within a very tight power budget. These challenges are addressed from the often conflicting perspectives of semiconductor design teams and commercial solutions providers of EDA construction tools, EDA analysis tools and semiconductor IP (SIP).

Design reuse is expected to be a key enabler for system designs in the 90's. Proponents claim that design reuse increases competitiveness through better quality, improved predictability and better productivity. On the other hand, skeptics say that design reuse is not realizable due to several barriers including rapid changes in technology, lack of standardized libraries and the presence of human, as opposed to technical barriers. Is design reuse a reality? How much is reused in practice? Where is it most applicable? Do concrete metrics exist for reusability? The panel will assess the track record of design reuse and discuss its status and future.

We present an algorithm for computing minimal-area fanout networks satisfying a delay constraint. We focus on one type of fanout network structure, the fanout chain. We show that, when using libraries designed for high-speed custom CMOS chips, the fanout chain typically produces minimal-area fanout networks for a given delay constraint. We then present fast, near-optimal algorithms to compute these fanout structures.

Synthesis has been used to generate layouts for MOS circuits having a wide range of complexity, from a few to thousands of transistors. Until recently, automatic layout was confined to cell based approaches using a library of pre-laid out cells, such as standard cells or sea-of-gates primitives. The direct use of arbitrary cells, or the quick generation of new library items, is now receiving increased attention. This paper presents an overview of the main issues specific to the cell generation of MOS digital circuits.

A description is given of CLEO, an automatic CMOS layout generator that takes as input an arbitrary sized circuit schematic and produces a CMOS layout as one or more horizontal rows of vertically oriented transistors. The layout can be controlled by specifying geometric constraints such as the number of rows desired, their specific heights and widths, and pins located on the region boundary. The tool was designed to lay out random logic sections of custom CMOS chips and is typically used with circuits ranging between 25 and 500 logic gates. CLEO obtains density close to handcrafted layout.>