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We present a spiking cortical column model based on neural associative memory, and demonstrate architectures for emulating the cortical column model with nanogrid molecular circuitry. We investigate a number of options for cost-effective hardware with digital CMOS and mixed-signal CMOL, a hybrid CMOS/nanogrid technology. We also give an example of a dynamic learning algorithm that is a suitable match to CMOL implementation.

Summary form only given. The possibilities of going to the next level after neural networks by creating new intelligent complex systems are discussed in This work. To create such complex systems, there are a number of important problems that must be solved. The problems presented are as follows: (a) scaling; (b) the degree of biological accuracy; (c) how to do system integration; and (d) hardware acceleration. Some examples of research in each area were also given in This work.

A useful enhanced vision system (EVS) for aircraft landing guidance not only has to provide the pilots a reliable image of the scene by fusing several sensor images in real time, but should also give them additional information such as attitude, navigation and hazard signals for safe landing in all weather conditions. Here, a biologically inspired EVS is proposed. The algorithms of the core modules of the systems, namely, the pre-processing and image retrieval are discussed in this paper. A FPGA version of the association network algorithm used in the application is discussed and its performance compared with the PC system.

When simulating very large, biologically plausible models on desktop computers, the memory bandwidth is the biggest bottleneck due to the significant performance difference between memory and processor. We did a performance analysis for different variations of the Palm association network implemented on Pentium 4 with VTune 6.1 performance analyzer. We also analyzed the performance of an FPGA implementing the same network. The FPGA performance is limited by the memory bandwidth and FPGA computation bandwidth, but continuous sequential memory fetch can be done more efficiently that in the Pentium 4.

A reinforcement learning based associative memory structure (RLAM) is proposed. In this structure, a one-layer feed forward Palm [Palm, G., 1980] model is applied to the networks. Instead of batch training, an on-line learning method is used to construct the memory. The networks are trained interactively according to reinforcement learning, which is biologically plausible. The experiment results show that the networks converge and generalize well.

The first half of this paper presents the design rationale for CNAPS, a specialized one-dimensional (1-D) processor array developed by Adaptive Solutions Inc. In this context, we discuss the problem of Amdahl's law which severely constrains special-purpose architectures. We also discuss specific architectural decisions such as the kind of parallelism, the computational precision of the processors, on-chip versus off-chip processor memory, and-most importantly-the interprocessor communication architecture. We argue that, for our particular set of applications, a 1-D architecture gives the best "bang for the buck", even when compared to the more traditional two-dimensional (2-D) architecture. The second half of this paper describes how several simple algorithms map to the CNAPS array. Our results show that the CNAPS 1-D array offers excellent performance over a range of IP algorithms. We also briefly look at the performance of CNAPS as a pattern recognition engine because many image processing and pattern recognition problems are intimately related.

In this panel session, the following topics are discussed: artificial intelligence in business; artificial intelligence in multimedia; neural networks as a tool for artificial intelligence: software engineering for knowledge-based systems: and artificial intelligence as a solution for software engineering.>

The motivation for the X1 architecture described was to develop inexpensive commercial hardware suitable for solving large, real-world problems. Such an architecture must be systems oriented and flexible enough to execute any neural network algorithm and work cooperatively with existing hardware and software. The early application of neural networks must proceed in conjunction with existing technologies, both hardware and software. Using state-of-the-art technology and innovative architectural techniques, the author's architecture approaches the speed and cost of analog systems while retaining much of the flexibility of large, general-purpose parallel machines. The author has aimed at a particular set of applications and has made cost-performance tradeoffs accordingly. The goal is an architecture that could be considered a general-purpose microprocessor for neurocomputing

Two neural network implementations of principal component analysis (PCA) are used to reduce the dimension of speech signals. The compressed signals are then used to train a feedforward classification network for vowel recognition. A comparison is made of classification performance, network size, and training time for networks trained with both compressed and uncompressed data. Results show that a significant reduction in training time, fivefold in the present case, can be achieved without a sacrifice in classifier accuracy. This reduction includes the time required to train the compression network. Thus, dimension reduction, as performed by unsupervised neural networks, is a viable tool for enhancing the efficiency of neural classifiers

In this paper, we describe how the memory management mechanisms of the Intel iAPX-432 are used to implement the visibility rules of Ada. At any point in the execution of an Ada® program on the 432, the program has a protected address space that corresponds exactly to the program's accessibility at the corresponding point in the program's source. This close match of architecture and language did not occur because the 432 was designed to execute Ada—it was not. Rather, both Ada and the 432 are the result of very similar design goals.To illustrate this point, we compare, in their support for Ada, the memory management mechanisms of the 432 to those of traditional computers. The most notable differences occur in heap-space management and multitasking. With respect to the former, we describe a degree of hardware/software cooperation that is not typical of other systems. In the latter area, we show how Ada's view of sharing is the same as the 432, but differs totally from the sharing permitted by traditional systems. A description of these differences provide some insight into the problems of implementing an Ada compiler for a traditional architecture.

The memory reference trace of a computation is modeled as a probabilistic process and the information content of that process is derived. Techniques are developed for analyzing the effectiveness of the addressing architecture and Memory/CPU traffic of existing machines with respect to the information theoretic bound for a given trace.