Spacecraft pose estimation is an essential computer vision application that can improve the autonomy of in-orbit operations. An ESA/Stanford competition brought out solutions that seem hardly compatible with the constraints imposed on spacecraft onboard computers. URSONet is among the best in the competition for its generalization capabilities but at the cost of a tremendous number of parameters and high computational complexity. In this paper, we propose Mobile-URSONet: a spacecraft pose estimation convolutional neural network with 178 times fewer parameters while degrading accuracy by no more than four times compared to URSONet.

In this paper, we analyze the performance and cost trade-off from selecting two representations of nodes when implementing the Aho-Corasick algorithm. This algorithm can be used for pattern matching in network-based intrusion detection systems such as Snort. Our analysis uses the Snort 2.9.7 rules set, which contains almost 26k patterns. Our methodology consists of code profiling and analysis, followed by the selection of a parameter to maximize a metric that combines clock cycles count and memory usage. The parameter determines which of two types of nodes is selected for each trie node. We show that it is possible to select the parameter to optimize the metric, which results in an improvement by up to 12× compared with the single node-type case.

This demo presents a virtual platform and its system design methodology for MPSoC ARM-Based FPGA applied on a use case. The focus is on the architectural exploration step and architecture implementation step. The platform is enabled by the SpaceStudio™tool suite, which incorporates novel research in virtual platform modeling, performance profiling, architectural exploration and system generation for MPSoC. The methodology is applied on the Image-Based Position Monitoring function of TwIRTee, a small three-wheeled rover. TwIRTee is the demonstrator of the INGEQUIP project conducted at the Institut de Recherche Technologique of Toulouse (IRT Saint- Exupéry).

We investigate trade-offs between traffic adaptation and VLSI architecture adaptation in C-RAN platforms. We propose a dynamic architectural scaling technique applied to interactive applications that require FFT computations. Our implementation results suggest Datapath scaling benefits applications with up to 4.89x improvement in GOPS/mW, while Fabric scaling can benefit Cloud Computing applications with up to 181.97x improvement in GOPS/mW, when compared to published methods. Improvements in network performance and energy-efficiency was achieved at a cost of built-in flexibility in the proposed VLSI architectures.

This paper introduces a new approach for finite-precision error modeling based on affine arithmetic. The paper demonstrates that there is a common hazard in affine arithmetic-based error modeling methods described in the literature. The hazard is linked to early substitution of the signal terms that emerge in operations such as multiplication and division. The paper proposes postponed substitution combined with function maximization to address this problem. The paper also proposes a modification in the error propagation process to enhance the error modeling accuracy. An existing word length optimization method is reproduced to evaluate the efficiency of this modification. The results demonstrate that the proposed modification can improve the hardware area results by up to 7.0% at the expense of negligible complexity overhead.

Bit-width allocation has a crucial impact on hardware efficiency and accuracy of fixed-point arithmetic circuits. This paper introduces a new accuracy-guaranteed word-length optimization approach for feed-forward fixed-point designs. This method uses affine arithmetic, which is a well-known analytical technique, for both range and precision analyses. This paper introduces an acceleration technique and two new semianalytical algorithms for precision analysis. While the first algorithm follows a progressive search strategy, the second one uses a tree-shaped search method for fractional width optimization. The algorithms offer two different time-complexity/cost efficiency tradeoffs. The first algorithm has polynomial complexity and achieves comparable results with existing heuristic approaches. The second algorithm has exponential complexity, but it achieves near-optimal results compared to the exhaustive search method. A commonly used set of case studies is used to evaluate the efficiency of the proposed techniques and algorithms in terms of optimization time and hardware cost. The first and second algorithms achieve 10.9% and 13.1% improvements in area, respectively, over uniform fractional width allocation. The proposed acceleration technique reduces the complexity of the fractional width selection problem by an average of 20.3%.

State-of-the-art System-on-Chip (SoC) consists of hundreds of processing elements, while trends in design of the next generation of SoC point to integration of thousand of processing elements, requiring high performance interconnect for high throughput communications. Optical on-chip interconnects are currently considered as one of the most promising paradigms for the design of such next generation Multi-Processors System on Chip (MPSoC). They enable significantly increased bandwidth, increased immunity to electromagnetic noise, decreased latency, and decreased power. Therefore, defining new architectures taking advantage of optical interconnects represents today a key issue for MPSoC designers. Moreover, new design methodologies, considering the design constraints specific to these architectures are mandatory. In this paper, we present a contention-free new architecture based on optical network on chip, called Optical Ring Network-on-Chip (ORNoC). We also show that our network scales well with both large 2D and 3D architectures. For the efficient design, we propose automatic wavelength-/waveguide assignment and demonstrate that the proposed architecture is capable of connecting 1296 nodes with only 102 waveguides and 64 wavelengths per waveguide.

Estimating the power consumption of System on Chip as early as possible in the design life cycle is important to meet the time to market requirements. For this purpose, most research is turning toward high-level models, like TLM, to estimate power earlier. This paper presents a high-level IP oriented power estimation methodology. The methodology separates the activity of the IP from the implementation. This allows the ability to easily create a model that can be used with different frequencies, layout and implementation technology. By using data gathered from the RTL a model can be created for high-level simulation that can take into account the technology and characteristics of the FPGA device. The methodology is presented in this paper with a processor and its local memory IP from Xilinx. Compared to estimations made at the RTL level, the resulting model gives accurate results of 15% with three to four order speedups and through different implementations.

Optical on-chip interconnects and 3D die stacking are currently considered to be two promising paradigms for the design of next generation Multi-Processors System on Chip architectures (MPSoC). New architectures based on these paradigms are currently emerging and new system-level approaches are required for their efficient design and prototype. The paper investigates a system-level flow for evaluating design feasibility, interconnect architecture performance and application execution efficiency as early as possible in the MPSoC design cycle.

Nowadays, designing systems using soft-core processors on FPGA is gaining in popularity and methodologies must arise to fulfill this new reality. This paper presents different techniques to develop instruction set simulators and its supportive components with SystemC to enable a fast FPGA development methodology without totally sacrificing the accuracy of the simulation. We have developed the Xilinx Microblaze software environment using ESL concepts at different abstractions to explore cycle accuracy versus simulation performance trade-offs. Results show that the low-level ESL model, while slower, is 6.8 times more accurate on average than the high-level model and as close as 3% from an on-FPGA execution. Conclusion tells us that a high-level model is thus appropriate for fast prototyping and debugging, while a lower-level model is more appropriate for performance estimation.

In todaypsilas high-tech world, intelligent video-surveillance is becoming a part of everyday life. In addition to minimizing the need for constant monitoring by an operator, it can automatically perform tasks such as accident detection or estimation of vehicle speed. A particularly useful algorithm for video surveillance is three-dimensional target tracking but, since it is both quite computationally expensive and requires the use of two cameras, it is seldom used. In this paper, we concentrate on accelerating an implementation of 3D tracking using a multiprocessor ASIP architecture based on the Tensilica Xtensa processor. Our experiments show that a speedup factor of 22 can be achieved using an extensible platform expressly optimized for this application as opposed to using a general-purpose processor.

Simulation monitoring tools are needed in hardware/software codesign for performance debugging, model validation and hardware/software partitioning purposes. Existing tools are either hardware- or software-centric and lack integrated and seamless co-monitoring. This paper presents a system-level co-monitoring tool that can monitor the computation and communication activities of SystemC user modules, as well as bus, memory and processor usage, on a variety of hardware/software embedded configurations that may include an RTOS. We also describe how performance metrics are generated during or after simulation and made accessible to users or external applications. Finally, experimental results show that such co-monitoring does not disturb the simulation's internal timing and only moderately increases the simulation's wall clock run time (by 11-22% for hardware/software partitioned architectures)

Analog and mixed signal (AMS) designs are important integrated circuits that are usually needed at the interface between the electronic system and the real world. Recently, several formal techniques have been introduced for AMS verification. In this paper, we propose a difference equations based bounded model checking approach for AMS systems. We define model checking using a combined system of difference equations for both the analog and digital parts, where the state space exploration algorithm is handled with Taylor approximations over interval domains. We illustrate our approach on the verification of several AMS designs including \Delta \Sigma modulator and oscillator circuits.

Formal methods have been advocated for the verification of digital design where correctness is proved mathematically. In contrast to digital designs, the verification of analog and mixed signal systems is a challenging task that requires lots of expertise and deep understanding of their behavior. In this paper, we present a run-time verification methodology based on monitoring the behavior (solution flow) of analog circuits. Monitors are deterministic timed automata that can be synthesized from temporal properties. For illustration purposes, we applied our methodology on the verification of the oscillation property of a tunnel diode oscillator.

Nowadays, the use of system level description languages is mandatory for the efficient design of complex systems. These description languages are exemplified by SystemC and SystemVerilog. In this paper, we propose a new .NET framework based system level modeling and simulation environment called Esys.NET (embedded systems design with .NET). It allows (1) cooperation - by enabling Web-based design and multi-language features, (2) easy systems specification task - by enabling integration of software components running application and operating systems and by alleviating memory management, (3) link to automatic refinement tools - by enabling translation of specification models into a standard intermediate format and annotation of specification models, and (4) comparative performances with existing environments.

A recent practice in the development of programmable SoC is the integration of configurable processors, since they offer an interesting compromise between purely software and hardware solutions. This paper proposes an adjustment to the current codesign approach to integrate this opportunity at the partitioning level. Since configurable processors seem to be an interesting option for NPU designs, we integrated into a system level exploration platform the support of an Xtensa processor for more investigation. As case studies, this paper illustrates the methodology for two realistic network-processing applications, for which interesting performances are obtained.

The next generation of tools for embedded systems design will represent a common arena for several cooperating groups. These tools will permit system design at a high abstraction level and enable automatic refinement through several abstraction levels to obtain the final prototype. To facilitate this evolution, we propose a new .Net Framework based system level modeling and simulation environment. This environment allows (1) cooperation -- by enabling web-based design and multi-language features, (2) easy systems specification task -- by enabling the integration of software components and by alleviating memory management and (3) the linking to automatic refinement tools -- by enabling the translation of model specifications into a standard intermediate format and by permitting the annotation of model specifications.

This paper proposes a methodology and a basic structure for the design of wrappers used to adapt cores for use as bus masters. The AMBA AHB protocol is used as a case study in this paper. The first step is to identify the responsibilities of the master. The designer must then develop correspondences between the behavior of the core and the requirements specified by the protocol. The final step is to build a state machine progressively, adding states to compensate for the core's inability to produce compliant behavior. An example of a wrapper for the ARM7TDMI is then presented.

This work attempts to enhance the support of embedded software modeling with SystemC 2.0. We propose a top-down approach that first lets designers specify their application in SystemC at a high abstraction level through a set of connected modules, and simulate the whole system. Then, the application is partitioned in two parts: software and hardware modules. Each partition can be connected to our platform that includes a commercial RTOS executed by an ARM ISS scheduled by the SystemC simulator. One of our major contributions is that we can easily move a module from hardware to software (and vice versa) to allow architectural exploration. These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

SystemC is a new open source library in C++ for developing cycle-accurate or more abstract models of software algorithms, hardware architecture and system-level designs. SystemC is meant to be an interoperable, modeling platform allowing seamless tool integration. Our objective is to evaluate the feasibility of linking a third party software to SystemC without modifying the SystemC source. We chose the development of a GUI as such an application. This application illustrates a set of applications following the observer pattern defined recently in software engineering. This class of applications can be loosely coupled to a platform designed following specific rules of software reuse.

In order to make software applications simpler to write and easier to maintain, a software digital signal-processing library that performs essential signal- and image-processing functions is an important part of every digital signal processor (DSP) developer's toolset. In general, such a library provides high-level interface and mechanisms, therefore, developers only need to know how to use algorithms, not the details of how they work. Complex signal transformations then become function calls, e.g., C-callable functions. Considering the two-dimensional (2-D) convolver function as an example of great significance for DSP's, this paper proposes to replace this software function by an emulation on a field-programmable gate array (FPGA) initially configured by software programming. Therefore, the exploration of the 2-D convolver's design space will provide guidelines for the development of a library of DSP-oriented hardware configurations intended to significantly speed up the performance of general DSP processors. Based on the specific convolver, and considering operators supported in the library as hardware accelerators, a series of tradeoffs for efficiently exploiting the bandwidth between the general-purpose DSP and accelerators are proposed. In terms of implementation, this paper explores the performance and architectural tradeoffs involved in the design of an FPGA-based 2-D convolution coprocessor for the TMS320C40 DSP microprocessor available from Texas Instruments Incorporated. However, the proposed concept is not limited to a particular processor.

Design and implementation of parallel pipelined Fast Fourier Transform (FFT), using Decimation in Frequency (DIF) algorithm on FPGAs is presented. The FFT core for 1024 complex data point is implemented on the X-CIM which is a Re-configurable Acceleration Subsystem (RAS) with a TMS320C4x DSP-processor and two XC4013 FPGA as its processing units. The proposed FFT machine is an alternative to the bit serial-parallel FFT algorithm using Distributed Arithmetic Look Up Table (DALUT) method. The advantage of proposed design is mainly in its cost effective and hardware-efficient parallel implementations of the N-point DFT, offering highly attractive throughput rates in relation to the conventional DSP processors. Moreover, the processor's data-path structure is independent of sampled data-paints, and it has a self-sorting property where the output is in properly ordered form. Our goal is to improve size-performance requirements of an FFT core function using modular and hierarchical VHDL description combined with IP-core library elements from Xilinx.

Tolerance to process-induced skew remains one of the major concerns in the design of large-area and highspeed clock distribution networks. Indeed, despite the availability of some efficient exact-zero skew algorithms that can be applied during circuit design, the clock skew remains an important performance limiting factor after chip manufacturing, and is of increasing concern for sub-micron technologies. This tutorial reviews the importance of the problem, its sources, as well as typical examples of existing solutions. Solutions range from design rule strategies to built-in self-compensation methods.

This paper addresses the problem of clocking large high-speed digital systems, as well as deterministic skew modeling, a related problem. In order to provide a reliable skew model, and to avoid the frequency limitation, we propose a novel approach that distributes the clock with an H-tree, whose branches are composed of minimum-sized inverters rather than metal. With such a structure, we obtain the highest clocking rate achievable with a given technology. Indeed, clock rates around 1 GHz are possible with a 1.2 /spl mu/m CMOS technology. From the skew modeling standpoint, we derive an analytic expression of the skew between two leaves of the H-tree, which we consider to be the difference in root-to-leaf delay pairs. The skew upper bound obtained has an order of complexity which, with respect to the H-tree size D, is the same as the one that may be derived from the Fisher and Kung model for both side-to-side and neighbor-to-neighbor communications, i.e., a /spl Omega/(D/sup 2/), whereas, the Steiglitz and Kugelmass probabilistic model predicts /spl Theta/(D/spl times//spl radic/LogD). In an H-tree implemented with metallic lines, the leaf-to-leaf skew is obviously bounded by the delay between the root and the leaves. However, with the logic based H-tree proposed here, we arrive at a nonobvious result, which states that the leaf-to-leaf skew grows faster than the root-to-leaf delay in presence of a uniform transistor time constant gradient. This paper also proposes generalizations of the skew model to (1) the case of chips in a wafer subject to a smooth, but nonuniform gradient and (2) the case of H-tree configurations mixing logic and interconnections; in this respect, this paper covers the H-tree configurations based on the combination of logic and interconnections.

We propose a new efficient constraint generation technique for 2-D mask compaction based on Branch-and-Bound Optimization (BBO). To assure separation in X and Y between rectangles in a layout, we generate the so called "diagonal" constraints in addition to the usual simple constraints in the X and Y directions. A diagonal constraint consist of two constraints, one in each dimension. Our method determines areas around the rectangles beyond which the diagonal (and the simple) constraints need not be generated, producing thus a nearly irredundant system of constraints. During BBO, the diagonal constraints are treated as dual constraints, in which case, one of the two component constraints of the dual can be deactivated. When a such constraint is deactivated, few additional constraints must be be added to assure a legal layout. The overall performance is still considerably improved, because there are fewer dual constraints. Proofs of sufficiency are based on a novel characterization of the 2-D constraint structure.

Propagation delays of signals on long interconnections and power consumption are very important limitations to the computing capacity of VLSI chips. Thus, this paper presents a low-power circuit for the fast propagation of signals on long interconnections in VLSI systems. Using electrical simulations with HSPICE guided by a heuristic, we present two designs that perform better in terms of speed and area than the conventional method. With both designs, power dissipation is reduced by 64%.>