A presentation as an invited speaker for IEEE Cyberworlds 2003, the International Conference on Cyberworlds, Singapore.

Banger is a parallel programming environment used by non-professional programmers to write explicitly parallel large-grain parallel programs. The goals of Banger are: 1. extreme ease of use, 2. immediate feedback, and 3. machine-independence. Banger is based on three principles: 1. separation of parallel programming-in-the-large from sequential programming-in-the-small, 2. separation of programming environment from target machine dependency, and 3. instant feedback to user wherever possible.

When the number of processors P is less than the number of tasks N in a parallel loop, the loop has to be executed in ⌈N/P⌉ rounds and the last round executes only (N mod P) tasks. In many cases, in the last round all but a few processors are idle, which causes a significant drop in performance. This performance drop becomes more and more detrimental as the number of processors increases. Loop spreading is a technique for restructuring parallel loops so as to balance parallel tasks on multiple processors. A spread loop runs at least as fast as the non-spread loop even when N mod P = 0, and shows no performance drop when N changes. We show how the method keeps the performance of the matrix multiplication and a simplex algorithm from decreasing as the size of input changes.

With the new advents of technology and the availability of microprocessors and minicomputers, parallel and distributed processing is gaining widespread acceptability. In such systems resources are shared among a number of processes. Accesses to the resources must be synchronized in order to guarantee proper operation of a system. In this research work, a measure, called maximal compatibility, is developed to measure the degree of concurrency (parallelism) a synchronization policy achieves. A set of accesses is considered compatible if it only contains accesses that are permitted to occur simultaneously. A policy is maximally compatible if it allows every compatible set of accesses to occur simultaneously and if the maximum number of requests is always satisfied without allowing incompatible accesses to occur simultaneously.

A translator system employing a partial compiler, intermediate language, and three-pass code generator is described that produces compact microcode for a class of horizontal microinstruction machines.

The demand for computer science education on the college campus is rapidly increasing. This is due to the ever expanding market for computer expertise in industry, government, and academia. The growth in the need for off-campus computer science instruction is also phenomenal. Professionals in areas other than computer science—engineering, business, etc.—need to acquire computing skills. Computer scientists need to continually keep pace with the rapidly evolving computer technology. This training must be available at sites remote from the college campus. In the era of overall decreasing college enrollments, computer science educators are being requested to service this off-campus market.

No abstract available.

This paper presents a new modular loop/ring architecture combining advantages of several earlier centralized and decentralized ring-structured loop networks while remaining simple. This is accomplished by introducing two major innovations: first, use of a separate control loop for control messages flowing between nodes and a loop controller; second, dynamically implementing partitionable segments between adjacent nodes and treating them as separate links for data transmission.

Methods are described to translate a certain machine-independent intermediate language (IML) to efficient microprograms for a class of horizontal microprogrammable machines. The IML is compiled directly from a high-level microprogramming language used to implement a virtual instruction set processor as a microprogram. The primary objective of the IML-to-host machine interface design is to facilitate language portability. Transportability is accomplished by use of a field description model and a macro expansion table which describe the host machine to the translator system. Register allocation scheme and control flow analysis are employed to allocate the symbolic variables of the IML to the general-purpose registers of the host machine. A set of 5-tuple microoperations (function, input, output, field, phase) is obtained with the aid of the field description model. Then a compaction algorithm is used to detect the parallelism of microoperations and to generate suboptimal code for a horizontal microprogrammable machine. The study concludes with a description of the effects of the above methods upon the quality of microcode produced for a specific commercial computer.

This paper presents a simplified approach to developing performance models for complex systems, such as distributed processing systems, and illustrates the approach by applying it to studying the performance of a new ring-structured microcomputer network. The approach utilizes both regression (curve-fitting) techniques and queueing theory analysis, and suggests that response times of the system studied can be closely approximated by a multiserver queueing model which is generalized to allow a noninteger number of servers. Both the approach and the approximate model developed appear to be applicable to a wide variety of systems.

Three contemporary pseudorandom number generators: Tausworthe, GFSR, and Lehmer are implemented on a 16-bit minicomputer. Practical comparisons are made in terms of 1) ease of implementation, 2) length of period, 3) execution speed, 4) program storage space, and 5) statistical quality. Although the results are conjectured to apply to any 16-bit word, limited memory capacity, and limited instruction set computer, the results for a PDP-11/05 indicate that the Lehmer generator satisfies criterion 5) but is slow and difficult to implement. The GFSR generator satisfies criteria 2) and 3) but is large, and the Tausworthe generator satisfies criteria 1) and 4) but can be statistically marginal.

The generalized feedback shift register pseudorandom number algorithm has several advantages over all other pseudorandom number generators. These advantages are: (1) it produces multidimensional pseudorandom numbers; (2) it has an arbitrarily long period independent of the word size of the computer on which it is implemented; (3) it is faster than other pseudorandom number generators; (4) the “same” floating-point pseudorandom number sequence is obtained on any machine, that is, the high order mantissa bits of each pseudorandom number agree on all machines— examples are given for IBM 360, Sperry-Rand-Univac 1108, Control Data 6000, and Hewlett-Packard 2100 series computers; (5) it can be coded in compiler languages (it is portable); (6) the algorithm is easily implemented in microcode and has been programmed for an Interdata computer.