We propose an anti-piracy security technique based on locking for analog and mixed-signal circuits designed in FD-SOI. We show that obfuscating the body-bias voltages of tunable transistors is an effective way for inducing high functionality corruption. The obfuscation is achieved by constituting a secret key from the concatenation of the input digital codes of the body-bias generators that produce the correct body-bias voltages. We also propose a slight modification of the body-bias generator that increases prohibitively the time complexity of counter-attacks aiming at finding an approximate key. The proposed locking scheme is demonstrated on a Σ$$ modulator used in highly-digitized RF receiver architectures.

Hardware Trojan (HT) insertion is a major security threat for electronic components that demand a high trust level. Several HT attack mechanisms have been demonstrated to date, and several HT prevention and detection countermeasures have been proposed to thwart HT attacks. Given the multitude of HT attack mechanisms, run-time monitors for HT detection are used as a last line of defense. In this paper, we propose a run-time monitoring methodology for HT attack mechanisms affecting the analog and mixed-signal (AMS) sections of an Integrated Circuit (IC). The methodology is based on the Symmetry-based Built-In Self-Test (SymBIST) principle that relies on distributing invariances across the IC and continuously checking for their compliance. Detection of various HT attacks are demonstrated on a Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) IP at transistor-level.

We propose a Hardware Trojan (HT) attack for analog circuits with its key characteristic being that it cannot be prevented or detected in the analog domain. The HT attack works in the context of Systems-on-Chip (SoCs) comprising both digital and analog Intellectual Property (IP) blocks. The attacker could be either the SoC integrator or the foundry. More specifically, the HT trigger is placed inside a dense digital IP block where it can be effectively hidden, whereas the HT payload is in the form of a digital pattern transported via the test bus or generated within the test bus, reaching the Design-for-Test (DfT) or programmability interface of the victim analog IP with the test bus. The HT payload unexpectedly activates the DfT and sets the victim analog IP into some possibly partial and undocumented test mode or changes the nominal programmability. The HT payload can be designed to result in performance degradation or complete malfunction, i.e., denial of service. We demonstrate this HT attack scenario on two analog IPs, namely a low-dropout (LDO) regulator using simulation and an RF receiver using hardware measurements.

We demonstrate an attack to break all analog circuit locking techniques that act upon the biasing of the circuit. The attack is based on re-synthesizing the biasing circuits and requires only the use of an optimization algorithm. It is generally applicable to any analog circuit class. For the attacker the method requires no in-depth understanding or analysis of the circuit. The attack is demonstrated on a bias-locked Low-Dropout (LDO) regulator. As the underlying optimization algorithm we employ a Genetic Algorithm (GA).

Fault diagnosis methodologies for analog circuits lag far behind those for their digital counterparts. In this paper, we show how the generic Symmetry-based Built-In Self-Test (BIST) (or SymBIST), originally proposed for defect-oriented post-manufacturing test and on-line test, can be seamlessly reused for the purpose of diagnosis. BIST can offer better insights into the circuit and, thereby, can assist diagnosis towards resolving ambiguity groups. Using SymBIST we demonstrate high diagnosis resolution and fast diagnosis cycle for an industrial Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC).

We treat the problem of analog integrated circuit (IC) obfuscation toward intellectual property (IP) protection against reverse engineering. Obfuscation is achieved by camouflaging the effective geometry of layout components via the use of fake contacts, which originally were proposed for gate camouflaging in digital ICs. We present a library of obfuscated layout components, we give recommendations for effective camouflaging, we discuss foreseen attacks and the achieved resiliency, and we propose security metrics for assessing the hardness of reverse engineering. The proposed methodology is demonstrated on an operational amplifier and an RF ΣΔ analog-to-digital converter (ADC).

We propose a Built-In Self-Test (BIST) paradigm for analog and mixed-signal (A/M-S) Integrated Circuits (ICs), called symmetry-based BIST (SymBIST). SymBIST exploits inherent symmetries in an A/M-S IC to construct signals that are invariant by default, and subsequently checks those signals against a tolerance window. Violation of invariant properties points to the occurrence of a defect or abnormal operation. SymBIST is designed to serve as a functional safety mechanism. It is reusable ranging from post-manufacturing test, where it targets defect detection, to on-line test in the field of operation, where it targets low-latency detection of transient failures and degradation due to aging. We demonstrate SymBIST on a Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC). SymBIST features high defect coverage, short test time, low overhead, zero performance penalty, and has a fully digital interface making it compatible with modern digital test access mechanisms.

We propose an antipiracy security approach for programmable analog and mixed-signal (AMS) integrated circuits (ICs). The security approach relies on functionality locking by leveraging the inherent programmability and utilizing the configuration settings as secret keys or, equivalently, the programming bits as key bits. When invalid keys are applied, the circuit is untuned and, as a result, its functionality breaks, i.e., at least one of the performances violates its specification. As long as the calibration algorithm that produces the configuration settings can be kept secret, the proposed approach can serve as a countermeasure against all types of counterfeiting, i.e., cloning, overbuilding, remarking, and recycling. An important advantage of the proposed approach is that it is lock-less. It leaves the design intact, there is no change to the design flow, and there are no performance penalty and no area or power overheads due to the lock operation. We demonstrate it on a$\Sigma \Delta $analog-to-digital converter (ADC) with 194-bit programmability and complex calibration algorithm used in the context of highly digitized, multistandard RF receivers.

In this paper, we demonstrate a security approach for the class of highly-programmable analog Integrated Circuits (ICs) that can be used as a countermeasure for unauthorized chip use and piracy. The approach relies on functionality locking, i.e. a lock mechanism is introduced into the design such that unless the correct key is provided the functionality breaks. We show that for highly-programmable analog ICs the programmable fabric can naturally be used as the lock mechanism. We demonstrate the approach on a multi-standard RF receiver with configuration settings of 64-bit words.

In this paper, we propose a defect-oriented Built-In Self-Test (BIST) paradigm for analog and mixed-signal (A/MS) Integrated Circuits (ICs), called symmetry-based BIST (Sym-BIST). SymBIST exploits inherent symmetries into the design to generate invariances that should hold true only in defect-free operation. Violation of any of these invariances points to defect detection. We demonstrate SymBIST on a 65nm 10-bit Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) IP by ST Microelectronics.

We present a Hardware Trojan (HT) attack scenario for analog circuits. The characteristic of this HT is that it does not reside inside the victim analog circuit. Instead, it resides on an independent digital circuit on the same die where it is triggered, yet its payload is applied only to the analog circuit after being transferred via the common test infrastructure and the test interface of the analog circuit. This HT attack cannot be detected or prevented in the analog domain and it exploits the dense digital circuit to hide effectively its footprint.

The increasing need for validating heterogeneous Systems on Chip (SoC) before their costly fabrication gives rise to the development of numerous virtual prototyping tools, allowing not only the modeling of such systems, but also the simulation of the environment in which they will be embedded, including the crucial software. SoC designers indeed require flexible simulation frameworks that follow a component-based approach and that cover a wide field of physical/engineering disciplines... and no questions asked about the simulation intrinsics. Furthermore, for SMEs, laboratories, and enthusiastic makers with limited funding, the cost of these frameworks makes them unaffordable, especially when the target system hardware is supposed to be Open Source too. In this paper, we detail the principles of an Open Source SystemC Multi-Disciplinary Virtual Prototyping (SystemC MDVP) framework, which directly tackles with all these issues. We introduce the key concepts and methodology (relationships between Models of Computation and overall synchronization techniques) and insist on the importance of a “correct by construction” global model elaboration that allows to generate the hierarchy of solvers that make up the final simulator. We then show that a new Model of Computation, Electrical Network, has been added to SystemC MDVP to handle components with non-linear beahviors. The paper concludes with a quick presentation of the echOpen project which aims at designing a low-cost portable echography device modeled and simulated with the presented principles.

This article presents a methodology for sizing transistors of a multistage, multipath capacitor-less feed-forward compensated operational amplifiers employed in advanced CMOS process implementation of continuous-time bandpass ΣA-modulators. This article describes the methodology: on system level, dealing with the placement of poles and zeros; and on the circuit level, discussing issues related to biasing, frequency response and other important performance metrics of the basic diff-pair. Algorithms are provided to simplify mathematical aspects of the work. The validity and the limitations of the proposed methodology are further discussed from the single-pole system used to model the individual amplification stages of the multistage amplifier. The worthiness of the proposed methodology in sizing the transistors of complex amplifier structures, such as the capacitor-less multistage, multipath feed-forward-compensated amplifiers is demonstrated using two design examples. A third-order amplifier with a dc gain of 52.6 dB and that reaches a unity-gain frequency of above 14 GHz while consuming only 5.6 mA from a 1-V supply; and a fourth-order amplifier with dc gain of 73.5 dB that achieves a 25.7-dB gain at 1 GHz while consuming 4.8 mW are designed in 28-nm CMOS FDSOI.

In this paper, we propose a hardware security methodology for mixed-signal Integrated Circuits (ICs). The proposed methodology can be used as a countermeasure for IC piracy, including counterfeiting and reverse engineering. It relies on logic locking of the digital section of the mixed-signal IC, such that unless the correct key is provided, the mixed-signal performance will be pushed outside of the acceptable specification range. We employ a state-of-the-art logic locking technique, called Stripped Functionality Logic Locking (SFLL). We show that strong security levels are achieved in both mixed-signal and digital domains. In addition, the proposed methodology presents several appealing properties. It is non-intrusive for the analog section, it incurs reasonable area and power overhead, it can be fully automated, and it is virtually applicable to a wide range of mixed-signal ICs. We demonstrate it on a ΣΔ Analog-to-Digital Converter (ADC).

This work presents a 4th-order multi-stage, multipath, feed-forward-compensated operational amplifier in 65 nm CMOS technology. It is designed to meet the requirements of a continuous-time bandpass ΣΔ modulator with multi-GHz sampling frequency. The designed amplifier is modular with each stage implemented based on a unit differential amplifier block and it meets its targets with smart placement of poles and zeros. The amplifier is simulated under the loading condition of a single-amplifier resonator which is in turn part of a 6th-order ΣΔ modulator. The unloaded amplifier reaches a unity-gain-frequency of 38.29 GHz and a DC gain of 58 dB. With a parallel load of 440 fF and 300 Ω, representing the maximum load, the op-amp, including common-mode and biasing circuits, consumes a total of 18.98 mA from a supply voltage of 1.2 V. It is unconditionally stable with a phase margin of 54° and has gains of 35 dB and 23 dB at 1 GHz and 2 GHz respectively.

The paper aims at stimulating a discussion on the prospect and potentiality of open source electronic design automation tools and open source hardware. We discuss the benefits and motivation, as well as the expected difficulties and shortcomings. Finally, we provide a representative list of efforts as of today specifically for analog and mixed-signal circuits and systems design and prototyping.

This paper proposes a fully-integrated solution for the PI compensation circuits in current-mode DC-DC converters used in automotive applications. In such applications, the switching frequencies are low and hence conventional PI compensation circuits employ large capacitors. The proposed analog/mixed-signal PI comprises an analog proportional amplifier and a digital integrator. The analog proportional amplifier provides the required response time and maintains system stability. The digital integrator block is used to eliminate the output voltage steady-state error. Simulink is used to model the proposed DC-DC buck converter on the system level. The proposed system is verified by full system level simulation. The digital part is synthesized with HDL coder and laid-out using 0.35 μm CMOS technology. The estimated silicon area of the proposed solution is about 0.1 mm2. This result highlights the simplicity and the capacity for integration of the proposed control loop along with its potential for seamless implementation into pre-existing solutions with minor modifications.

Substrate noise coupling due to minority carriers propagation in smart power integrated circuit becomes a critical issue specially for high voltage applications. Computer-Aided-Design modeling methodology for substrate parasitic-immune design was introduced. It is based on constructing a 3D substrate equivalent network. The substrate equivalent network consists of models of diodes and resistors that are capable of preserving the continuity of minority carriers. In this paper, an optimized meshing topology for substrate modeling is introduced. This meshing topology contributes significantly in the extracted component reduction and hence speeds up the simulation while improving the convergence of the simulator. A typical NPN bipolar transistor is used as case study. Comparing the proposed meshing topology to the basic meshing topology, the number of extracted components is reduced by 78% and the simulation time is lowered by 88%. SPICE-like analysis results confirm the accuracy of modeling approach with an acceptable relevant error (<;10%) compared to standard model. With the proposed meshing topology, it is feasible to model the substrate parasitic of more complex smart power integrated circuit.

This paper presents a 1.1-V 200 MS/s pipeline ADC with 70 dB signal-to-noise-plus-distortion ratio (SNDR) and 54 mW power consumption. This performance is enabled by employing low gain amplifiers in the first two pipelined stages and digitally calibrate the inter-stage gain errors in the background using split ADC technique. To calibrate multistage in split ADC, Slope Mismatch Averaging (SMA) is used with a programmable-residue in the first stage. A low voltage two stage amplifier is used with feedforward compensation in its main loop and the common mode feedback (CMFB) loop to decrease the power consumption. Implemented in 40 nm CMOS, the ADC achieves more than 11 ENOB in post-layout simulation results.

A bottom plate sampling switch sharing technique is proposed to enable split ADC calibration with high frequency inputs for Sample and Hold Amplifier-less (SHA-less) pipeline ADCs. The shared bottom plate switch ensures that both halves of the ADC sample the input at the same time, which restores the calibration accuracy for fast varying inputs without the presence of a front-end SHA, thereby significantly reducing area and power consumption. For further power reduction, a feedforward two stage amplifier has been used to push the speed of the amplifier at lower current consumption and low supply voltage. A 12-bit 200 MS/s pipeline ADC has been designed in 40 nm CMOS technology, and the transistor level simulations of the ADC prove the efficiency of the proposed technique to restore the split ADC calibration accuracy in SHA-less pipeline ADCs.

This paper presents a structured DC analysis methodology for analog circuit verification. The electrical simulator, usually executed to perform verification, is here replaced by a nonlinear DC solver based on the analysis bipartite graph. The analysis bipartite graph, associated to a circuit, is a formal representation of the circuit DC behavior. Thus, the analysis bipartite graph evaluation provides transistors currents and internal nodes voltages to meet the Kirchhoff's laws in the circuit. Currents and voltages are computed by dedicated operators using the fixed point iteration algorithm. Computed results accuracy is guaranteed by the standard transistor models used within the operators. The proposed verification methodology is efficiently applied on a folded cascode amplifier with several technologies.

The goal of this paper is to provide design considerations for the use of low gain amplifier presents in the Multiplying Analog-to-Digital Converter (MDAC) of pipelined ADCs with gain error correction in the digital domain. Using low gain amplifier in the MDAC makes the pipelined ADC more susceptible to gain variation and harmonic distortion, impacting the ADC performance. Theory and simulations are presented to provide design insight into the trade-off between minimum gain and its variations to preserve the calibrated ADC performance. These considerations are demonstrated on the MDAC of a 12 bit digitally calibrated pipelined ADC designed in 40nm CMOS technology.

The paper presents the principles, techniques and tools for the efficient modeling and simulation, at the component level, of an heterogeneous system composed of Wireless Sensor Network nodes that exhibits complex multi-discipline feedback loops that are likely to be found in many state-of-the-art applications such as cyber-physical systems. A Precollision Mitigation Braking System (PMBS) is used as a pragmatic case study to validate the whole approach. The component models presented (60 GHz communication channel, QPSK RF transceiver, CMOS video sensor, digital microcontroller, simplified car kinetic engine) are written in SystemC and its analog Mixed-Signal extensions, SystemC-AMS, and belong to five distinct yet highly interwoven disciplines: newtonian mechanics, op to-electronics, analog RF, digital and embedded software. The paper clearly exhibits the complex multi-discipline feed- back loop of this automotive application and the related model composability issues. Using the opto-electrical stimulus and the received RF inter-vehicle data, a car is able to exploit its environmental data to autonomously adjust its own velocity. This adjustment impacts the physical environment that in turns modifies the RF communication conditions. Results show that this holistic first-order virtual prototype can be advantageously used to jointly develop the final embedded software and to refine any of its hardware component part.

A foreground digital calibration technique for pipelined ADC is proposed which accounts for linear error correction, while an error estimation technique for amplifier non-linearity is suggested as a reference for non-linear error correction. The calibration algorithm is based on applying a slow input to the ADC to automatically correct for linear errors, while depending on the accuracy of Digital Error Correction (DEC) to estimate and correct for non-linear errors. The proposed calibration scheme is demonstrated for an 11 bit pipelined ADC, and gives SNDR improvement over 30 dB, while using low specifications residue amplifier to reduce power consumption.

A methodology for the design of Continuous-Time (CT) Sigma-Delta (ΣΔ) modulators with VCO-based quantizer is proposed. The coefficients of the CT ΣΔ modulator are accurately calculated such that the noise transfer function of the modulator is exactly the same as a Discrete-Time (DT) ΣΔ modulator of the same order. The proposed design method takes into account loop-delay compensation as well as the shape of the feedback Digital-to-Analog Converter (DAC) signal. VCO non-idealities such as non-linear Kvcoand phase noise are studied. Several design examples for different modulator orders and feedback DAC signal shapes are given to validate the proposed methodology.

A SigmaDelta GmC integrator refinement flow is presented. The classically simplified GmC integrator small-signal model was upgraded to be extremely accurate by considering the complete transistor small-signal model. A circuit-level knowledge-based tool was used to execute the designer defined sizing procedure and to extract small signal parameters. By associating the symbolic transfer function to small-signal parameters, the flow, entirely implemented with C++, is able to compute poles and zeros to permit precise behavioral simulations. A 2ndorder SigmaDelta modulator was chosen to visualize performance degradations while the specifications were not achievable.

This paper presents a mixed equation-based and simulation-based design methodology for continuous-time sigma-delta modulators from high level specifications down to layout. The calculation and scaling of the sigma-delta coefficients as well as circuit sizing and layout generation are implemented in the same analog design environment CAIRO+. The design of a complete third order current-mode continuous-time sigma-delta modulator is taken as an example to show the effectiveness of the proposed design methodology.

This paper presents the complete design methodology of a very low-voltage /spl Delta//spl Sigma/ third-order modulator from high-level specifications down to layout. Behavioral models taking into account cell nonidealities are developed and used to map performance specifications to lower levels. Emphasis has been made on eventual design reuse through design plans and layout templates in a layout-oriented circuit design approach. The modulator has been designed for two different technologies demonstrating the suitability of the methodology for very high performance mixed-signal circuits. Moreover the same design knowledge has been successfully reused in another fourth-order modulator.

This paper presents a methodology for the synthesis of high performance analog circuits. Layout parasitics are estimated and compensated during circuit sizing. Physical layout constraints are thus taken into consideration early in the design. This approach shortens the overall design time by avoiding laborious sizing-layout iterations. The approach has been implemented using two knowledge-based tools dedicated to analog circuit sizing and layout generation. An example of a high performance OTA is presented to illustrate the effectiveness of the approach.