Quantum-dot fabrication and characterization is a well-established technology, which is used in photonics, quantum optics, and nanoelectronics. Four quantum-dots placed at the corners of a square form a unit cell, which can hold a bit of information and serve as a basis for quantum-dot cellular automata (QCA) nanoelectronic circuits. Although several basic QCA circuits have been designed, fabricated, and tested, proving that quantum-dots can form functional, fast and low-power nanoelectronic circuits, QCA nanoelectronics still remain at its infancy. One of the reasons for this is the lack of design automation tools, which will facilitate the systematic design of large QCA circuits that contemporary applications demand. Here we present novel, programmable QCA circuits, which are based on crossbar architecture. These circuits can be programmed to implement any Boolean function in analogy to CMOS field-programmable gate arrays and open the road that will lead to full design automation of QCA nanoelectronic circuits. Using this architecture we designed and simulated QCA circuits that proved to be area efficient, stable, and reliable.

Cellular automata (CAs) have been widely used to model and simulate physical systems and processes. CAs have also been successfully used as a VLSI architecture that proved to be very efficient at least in terms of silicon-area utilization and clock-speed maximization. Quantum cellular automata (QCAs) as one of the promising emerging technologies for nanoscale and quantum computing circuit implementation, provides very high scale integration, very high switching frequency and extremely low power characteristics. In this paper we present a new automated design architecture and a tool, namely DATICAQ (Design Automation Tool of 1-D CAs using QCAs), that builds a bridge between 1-D CAs as models of physical systems and processes and 1-D QCAs as nanoelectronic architecture. The QCA implementation of CAs not only drives the already developed CAs circuits to the nanoelectronics era but improves their performance significantly. The inputs of the proposed architecture are CA dimensionality, size, local rule, and initial and boundary conditions imposed by the particular problem. DATICAQ produces as output the layout of the QCA implementation of the particular 1-D CA model. Simulations of CA models for zero and periodic boundary conditions and the corresponding QCA circuits showed that the CA models have been successfully implemented.

The increasing complexity of computer networks calls for the development of new models for their simulation. Cellular automata (CAs) are a well-known and successful model for complex systems. This paper presents a system for modeling and simulation of computer networks based on CAs. More specifically, a 2D NaSch CA computer network model has been developed, and several networks were simulated. Algorithms for connectivity evaluation, system reliability evaluation, and shortest path computation in a computer network have also been implemented. Our system, called Net_CA system, was designed and developed as an interactive tool that offers automated modeling with the assistance of a dynamic and user-friendly graphical environment. The proposed system also produces automatically synthesizable very high speed integrated circuits hardware description language code leading to the parallel hardware implementation of the aformentioned CA algorithms. In terms of circuit design and layout, ease of mask generation, silicon area utilization, and maximization of achievable clock speed, CAs are perhaps the computational structures best suited for a fully parallel very large scale integrated realization. The simulation algorithms developed in the present paper offer high flexibility. Furthermore, connection reliability and other important parameters are inputs to the algorithms, rendering Net_CA a very reliable and fast simulator for wireless networks, ad hoc networks, and generally, for low connection reliability networks.

Recent advances in electronic technology integration coupled with increasing needs for more services in portable communications favors the development of high performance dual-mode terminals. We present the complete architecture implementation of the GMSK/GFSK modulator/demodulator including the FIR filters design. The main features of the modulator/demodulator and the architectural implementation of FIR filters are described. The interface with ASPIS processor and A/D & D/A converters is also described in detail manner. The whole architecture of the modulator/demodulator was described by VHDL hardware language, synthesised and implemented in Xilinx environment.