The proliferation of transmissions in the RF spectrum demands robust and responsive signal analysis techniques to detect and label malicious activity. Traditional methods struggle to balance sensitivity and accuracy in real-time. This paper introduces Nomad, a modular system that combines global spectral pattern recognition with localized energy detection and classic signal processing methods for efficient and accurate RF analysis. Nomad's innovative architecture facilitates rapid development and deployment, while its intuitive visualizations provide actionable insights into even weak signals within complex RF environments.

Digital filter sharpening aims to improve filtering by cascading structures employing multiple use of an original prototype's unchanged coefficient set. Starting with a visitor-designed FIR prototype, we demonstrate the operation of three different sharpening methods, comparing their various advantages and shortcomings. Two tools are employed: a Simulink model, facilitating visual examination of virtual instrument displays, and a MATLAB package that provides a compact equivalent filter model of the sharpened resultant.

Acoustic feedback control continues to be a challenging problem due to the emerging form factors in advanced hearing aids (HAs) and hearables. In this paper, we present a novel use of well-known all-pass filters in a network to perform frequency warping that we call "freping." Freping helps in breaking the Nyquist stability criterion and improves adaptive feedback cancellation (AFC). Based on informal subjective assessments, distortions due to freping are fairly benign. While common objective metrics like the perceptual evaluation of speech quality (PESQ) and the hearing-aid speech quality index (HASQI) may not adequately capture distortions due to freping and acoustic feedback artifacts from a perceptual perspective, they are still instructive in assessing the proposed method. We demonstrate quality improvements with freping for a basic AFC (PESQ: 2.56 to 3.52 and HASQI: 0.65 to 0.78) at a gain setting of 20; and an advanced AFC (PESQ: 2.75 to 3.17 and HASQI: 0.66 to 0.73) for a gain of 30. From our investigations, freping provides larger improvement for basic AFC, but still improves overall system performance for many AFC approaches.

This study presents two hardware architectures for the efficient implementation of fast Fourier transform (FFT) based on the combined Good–Thomas and Winograd Fourier transform algorithms. The combined algorithms require fewer multiplications compared with the other FFT algorithms by eliminating twiddle factor multiplications. Two hardware architectures are presented: one is a fully‐pipelined architecture using multi‐dimensional Chinese remainder theorem for a high‐throughput implementation and the other is a time‐multiplexed architecture, which utilises the folding transformation for the compact realisation of short‐length Winograd Fourier transforms. Both designs are fully‐parameterisable and have been verified against their synthesisable Verilog descriptions. The characteristics and the implementation results of the two hardware architectures on a Xilinx field‐programmable gate array are presented. To the best of the authors' knowledge, this study presents the first hardware realisation of FFT based on the combined Good–Thomas and Winograd FFT algorithms. The application of the proposed FFT architectures in the physical layer of the long‐term evolution wireless standard is discussed.

This letter shows that, for arbitrary M-fold polyphase decompositions, the polyphase components of digital fractional-delay (FD) filters correspond to FD filters as well, but with different delays and gains. For even values of M, the components also have additional and different phase offsets. The letter also discusses the application of these results to the optimization of high-order filters with few unknowns.

This paper investigates the filter bank (FB) based selection diversity combining as well as linear equalization for single carrier (SC)transmissions over frequency selective channels. In contrast to the multicarrier carrier (MC) transmissions, e.g., OFDM, the FB based approach avoids the use of cyclic prefix (CP) or guard band and offers a number of superior properties such as synchronization, and peak to average power ratio (PAPR), etc. However, due to the lack of practical diversity techniques and cost effective equalizers, the broadband SC signal can hardly be deployed under highly dispersive channel environment. We propose a practical FB based selection diversity based on non-maximally decimated filter banks with perfect reconstruction support (PR-NMDFB) with its companion linear equalizer in the FB transformed domain. We shall give detailed minimum mean square error (MMSE) and bit error rate (BER) analysis and compare it to the optimal maximum ratio combining (MRC) solution.

This paper describes a step forward in the utilization of non-maximally decimated filter banks (NMDFBs) with perfect reconstruction (PR) property in modern software defined radios. In particular, here we apply the tone reservation (TR) technique for reducing the peak to average power ratio (PAPR) to a PR analysis-synthesis chain which has been designed for a combined Third Generation Partnership Protocol (3GPP), Long Term Evolution (LTE) and Universal Mobile Telecommunications System (UMTS) digital up converter (DUC). The DUC architecture was proposed in an early paper and the efficacy of the design has been tested in an industrial environment and verified for being prototyped on real chips. Similar to orthogonal frequency division multiplexing (OFDM) systems, the proposed architecture is affected by the PAPR issue. Here we borrow the TR reservation technique which was developed in the OFDM scenario and we apply it to the proposed architecture. Of course, given the difference between OFDM and NMDFB systems, different design constraints have to be taken into account. Preliminary simulation results show good performance in reducing the crest factor (CF) which, along with the limited workload required by the proposed architecture, encourage us to implement this solution in the next generation of communication chips.

The CIC filter is often used as a decimating filter to simultaneously reduce bandwidth and sample rate of the time series obtained at the output of a 1-bit Sigma-Delta con-verter. The conventional motivation for using the CIC is that the filtering is performed with only registers and adders, there being no multipliers in the CIC filter chain. We note that every FIR filter processing the output of a 1-bit sigma delta convert-er can also be implemented without multipliers. The CIC filter does not take advantage of the fact that the input samples are limited to two input levels. It is possible to design FIR filters using the two level input signal to form efficient multiply free filters that compare favorably with the CIC filter. We present here a partition of the filter and down sampling task into a cascade of a polyphase pre-filter that performs a first band-width and sample rate reduction without multiplies followed by a reduced sample rate CIC filter performing the second bandwidth and sample rate reduction. Operating the second filter as a CIC at a reduced output rate reduces its workload and the bit width required by its accumulators.

There are number of software defined radio applications in which a radio receiver must access multiple simultaneous channels with different channel bandwidths. This paper presents the architecture of a novel and extremely efficient implementation of such a channelizer. The receiver described here simultaneously forms ten 5-MHz wide channels and one hundred 0.5 MHz wide channels spanning a 50 MHz input bandwidth. Multirate signal processing techniques are used throughout the processing chain to obtain extremely low processing computational workload.

In this paper, we propose a robust data-aided carrier frequency offset (CFO) tracking algorithm for orthogonal frequency division multiplexing (OFDM) system. The problem is solved as a sequence of estimation and correction steps. We find the major contributors to the CFO measurement uncertainty are the additive white noise together with the inter-carrier interference (ICI). Our derivation results show the noise variance can be reduced via averaging while the ICI introduced uncertainty can be decreased by iterative CFO compensations. These considerations lead us to a Type-2 correction loop. Theoretical analysis and simulation results show our proposed algorithm is robust and able to compensate and track comparably large CFO.

A digitally controlled sampled data delay line is implemented with recursive all-pass filter sections. This is in marked contrast to the standard implementation of programmable time delays that use fixed non-recursive polyphase stages or adjustable Farrow FIR filters. The recursive filter exhibits an equal-ripple approximation to constant group delay. The phase slope is programmable to present a continuously variable time delay network. Applications of a continuously adjustable, linear- time delay structure offers unique signal processing options to address various communication system tasks. These include timing recovery in DSP and FPGA based receivers, adaptive beam forming and steering, communication systems channel modeling, and reverberation modeling in acoustic chambers and instruments.

Digital signal processing techniques are applied to maximum likelihood carrier phase synchronization for QPSK and QAM in an all-digital sampled data receiver. To achieve the flexibility required by modern software defined radios (SDRs), this task must either be performed in a DSP processor (reconfigurable software) or in an FPGA (reconfigurable hardware). This paper describes the design process for an FPGA-based design and summarizes the FPGA resources required for QPSK carrier phase synchronization.

This paper describes the use of a polyphase filterbank to perform the interpolations required for symbol timing synchronization in a sampled-data receiver. The polyphase filterbank possesses advantages over architectures based on separate matched and interpolation filters. Interpolations are realized by filterbank index selection and a separate interpolating filter following the matched filter is not required. Maximum likelihood timing synchronization techniques can be easily incorporated into the polyphase filter bank in a natural way. An M-stage polyphase filterbank with input data sampled at approximately N samples/symbol can be used in a loop that operates at MN samples/symbol, N samples/symbol, or 1 sample/symbol. When operating at 1 sample/symbol, auxiliary control must also be included to adjust the clocking of data into the filter bank to account for small differences in the sample clock and N times the data clock. Examples are presented to illustrate loop performance and control.

Software defined radios (SDR) are highly configurable hardware platforms that provide the technology for realizing the rapidly expanding third (and future) generation digital wireless communication infrastructure. Many sophisticated signal processing tasks are performed in a SDR, including advanced compression algorithms, power control, channel estimation, equalization, forward error control and protocol management. While there is a plethora of silicon alternatives available for implementing the various functions in a SDR, field programmable gate arrays (FPGAs) are an attractive option for many of these tasks for reasons of performance, power consumption and configurability. Amongst the more complex tasks performed in a high data rate wireless system is synchronization. This paper is about carrier and timing synchronization in SDRs using FPGA based signal processors. We describe and examine a QPSK Costas loop for performing coherent demodulation, and report on the implications of an FPGA mechanization. Symbol timing recovery is addressed using a differential matched filter control system. A tutorial style approach is adopted to describe the operation of the timing recovery loop and considerations for FPGA implementation are outlined.

This paper investigates an architectural option for constructing high sample-rate narrow-band single rate and multi-rate filters using Xilinx field programmable gate array (FPGA) technology. Sigma-delta modulation encoding is applied to the input data in order to effect a reduction in the precision of the arithmetic units in the filter. This is done without compromising the signal integrity within the band of interest. The implementation provides a significant savings in device logic resources in comparison to other techniques that provide the same functionality. The sigma-delta preprocessor is described and its implementation using XC4000 FPGAs is reported. The architecture of the reduced precision filter is presented and its FPGA realization described.

The performance of a signal-processing system is frequently limited by the dynamic range of the system's analog-to-digital conversion. In a previous paper (1987), W.H. McKnight, J.M. Speiser, and H.J. Whitehouse introduced the concept of linear-predictive analog-to-digital conversion and presented both open- and closed-loop architectures for such converters. To provide a real-time implementation of the required predictors, they proposed a transversal filter implementation of fixed-weight predictors. The authors extend the previous results by modifying the filter weights to accommodate the quantization noise present at the input to the prediction filter.>

A synthetic array radar (SAR) image is formed by processing a data base collected by an aircraft flying an array length while periodically interrogating the image field with a sequence of transmitted pulses. The length of the array, hence the resolution of the map is limited by quadratic phase terms which are accumulated along the array path. We will show in this paper, that this quadratic term is due in part to the uniform temporal sampling and can be significantly reduced by an observer adaptive sampling technique. This technique is particularly useful for minimizing the effects of aircraft maneauvers on the image depth of field.