Demo Data from VLDB 2026 / reviewers in the wild / expert
Haruhisa Kashiwagi
dblp:06/4388
· DBLP profile ↗
1ranked-venue papers
0as first author
0since 2021 · last 2007
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 88% Integrated circuit design · 12% |
Topics — the 4 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation
system-level design |
0.1 | 1 | 2007 | TLM: Crossing Over From Buzz To Adoption · DAC 2007 |
Electronic design automation › system-level design › high-level system modeling
transaction-level modeling |
0.1 | 1 | 2007 | TLM: Crossing Over From Buzz To Adoption · DAC 2007 |
Electronic design automation › hardware verification and test
hardware verification |
0.0 | 1 | 2007 | TLM: Crossing Over From Buzz To Adoption · DAC 2007 |
Integrated circuit design
system-on-chip |
0.0 | 1 | 2007 | TLM: Crossing Over From Buzz To Adoption · DAC 2007 |
Methods — techniques the papers use, named apart from their topics
systemc · 0.1
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2007 | TLM: Crossing Over From Buzz To AdoptionabstractTransaction-level modeling --- originally used decades ago in the development of telecommunications network architecture --- is now widely used in SoC design. Why? Because the modern SoC is now so complex that systematic modeling and analysis are required to devise the optimal chip architecture. The architectural model is the essential platform that kick-starts two other key tasks --- verification testbench development and software development. In addition, the interoperability imperatives of SoC design and verification, IP reuse, software development, and system evaluation and integration have driven the replacement of proprietary transaction-level modeling methodologies by a TLM standard that leverages the power of SystemC. The standard --- devised by the Open SystemC Initiative (OSCI) in collaboration with the Open Core Protocol International Partnership (OCP-IP) --- covers the multiple levels of abstraction required for all of the foregoing tasks. Francine Bacchini, Daniel Gajski, Laurent Maillet-Contoz, Haruhisa Kashiwagi, Jack Donovan, Tommi Mäkeläinen, Jack Greenbaum, Rishiyur S. Nikhil |
DAC | 4 |