Demo Data from VLDB 2026 / reviewers in the wild / expert
K. M. Adams
dblp:06/5530
· DBLP profile ↗
2ranked-venue papers
0as first author
0since 2021 · last 1995
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Reconfigurable computing and FPGAs · 77% Interconnection networks and networks-on-chip · 23% |
Topics — the 2 heaviest of 2, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Reconfigurable computing and FPGAs
FPGA-based instrumentation |
0.0 | 1 | 1995 | An SBus Monitor Board · FPGA 1995 |
Interconnection networks and networks-on-chip › bus-based interconnection
system bus |
0.0 | 1 | 1995 | An SBus Monitor Board · FPGA 1995 |
Methods — techniques the papers use, named apart from their topics
field-programmable gate array · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1995 | An SBus Multi-Tracer and its applicationsabstractAn SBus Multi Tracer (MT) is described, which is based on our previously developed SBus monitoring board (SMB), which can provide timing diagrams for all SBus signals. However, just like any other logic analyzer or a bus analyzer its trace length is limited by the board memory and it is difficult to cope with multi occurrences of trigger patterns in a single application. An effective answer to this problem is to design an SBus Multi Tracer instead of increasing the size of the board memory. An SMB with MT achieves multiple partitions of its tracing memory by tracing a fixed number of events after each trigger. In this way it provides systematic timing information for a series of pattern occurrences in a sequence of system operations. The possible operation of the SMB is enabled by a built-in Field Programmable Gate Array (FPGA) chip, which has access to all SBus signals, and can easily be reconfigured to provide additional triggering patterns. H. A. Xie, Kevin E. Forward, K. M. Adams, Suthikshn Kumar |
Asian Test Symposium | 3 |
| 1995 | An SBus Monitor BoardabstractDuring the development of computer peripherals which interface to the processor via the system bus it is often necessary to acquire the signals on the bus at the hardware level. It is difficult to attach general-purpose logic analysers and in-circuit emulators to a multiple pin bus connector and hence it is not practical to catch all the bus data required to ensure that such signals are in accordance with the bus specification. Hence a given connector specific bus monitor board is a necessary instrument to attach to the system motherboard in order to monitor all bus activities. A connector specific bus monitor board provides an efficient resource with which to study the internal philosophy of system software, the software implementation process for different communication layers, and to provide debugging for hardware developers. The bus monitor board described here is designed to attach to a SUN SBus and is similar to the Transformable Computer, which appeared recently, in that its architecture is reconfigurable via the use of a Field Programmable Gate Array (FPGA). It can be programmed to customise it to various users' specific needs. It differs from the Transformable Computer in that although it can be programmed to function as a coprocessor its primary function is dedicated SBus Monitoring. It is less costly than a Transformable Computer. H. A. Xie, Kevin E. Forward, K. M. Adams, D. Leask |
FPGA | 3 |