Due to technology scaling, electromigration (EM) signoff has become increasingly difficult, mainly due to the use of inaccurate methods for EM assessment, such as the empirical Black's model. In this paper, we present a novel finite-differencebased approach for power grid EM checking using physics-based models, that can account for process, voltage, and temperature variations across the die. Our main contribution is to extend existing physical models for EM in metal branches to track EM degradation in multibranch interconnect trees. The extended model is represented as a homogeneous linear time invariant system. We also detect early failures and account for their impact on grid lifetime. We speed up our implementation by proposing a macromodeling-based filtering scheme and a predictor-based approach. Our results, for a number of IBM power grid benchmarks, confirm that Black's model is overly inaccurate. The lifetimes found using our physics-based approach are on average 2.75× longer than those based on a (calibrated) Black's model, as extended to handle mesh power grids. With a maximum runtime of 2.3 h among all the IBM benchmarks, our method appears to be suitable for very large scale integration circuits.

Electromigration (EM) is a key reliability concern in chip power/ ground (p/g) grids, which has been exacerbated by the high current levels and narrow metal lines in modern grids. EM checking is expensive due to the large sizes of modern p/g grids and is also inherently difficult due to the complex nature of the EM phenomenon. Traditional EM checking, based on empirical models, cannot capture the complexity of EM and better models are needed for accurate prediction. Thus, recent physics-based EM models have been proposed, which remain computationally expensive because they require solution of a system of partial differential equations (PDEs). In this paper, we propose a fast and scalable methodology for power grid EM verification, building on previous physics-based models. We first convert the PDE system to a succession of homogeneous linear time invariant (LTI) systems. Because these systems are found to be stiff, we numerically integrate them using optimized variable-step backward differentiation formulas (BDFs). Our method, for a number of IBM power grids and internal benchmarks, achieves an average speed-up of over 20x as compared to previously published work and has a runtime of only about 8 minutes for a 4 million node grid.

Due to technology scaling, electromigration (EM) signoff has become increasingly difficult, mainly due to the use of inaccurate methods for EM assessment, such as the empirical Black's model. In this paper, we present a novel approach for EM checking using physics-based models of EM degradation, which effectively removes the inaccuracy, with negligible impact on run-time. Our main contribution is to extend the existing physical models for EMin metal branches to track the degradation in multi-branch interconnect trees. We also propose effective filtering and predictor-based schemes to speed up our implementation, with minimal impact on accuracy. Our results, for a number of IBM power grid benchmarks, confirm that Black's model is overly inaccurate. The lifetimes found using our physics-based approach are on average 3× longer than those based on a (calibrated) Black's model, such as currently used in industry. For the two largest IBM benchmarks (700K branches each), our runtime is comparable to that of the Black's based approach, requiring 3 hours for the largest grid.

Electromigration (EM) in on-die metal lines is becoming a significant problem in modern integrated circuits technology. Due to the high levels of current density on the die, the large number of metal lines, and the inherent conservatism in classical full-chip EM models, designers are finding it very hard to meet the area and design specs while guaranteeing EM reliability. The EM problem is most significant in power grid lines, because unlike signal and clock lines, they do not benefit from healing due to their mostly unidirectional currents. In this paper, we develop a new model, referred to as the mesh model, for power grid EM checking which takes into account the inherent redundancy of its mesh structure while determining the reliability. To implement the mesh model, we also develop a framework to estimate the change in statistics of an interconnect as its effective-EM current varies. In order to overcome the conservative assumptions that designers usually make about chip workloads, we also propose a novel vectorless mesh model technique to estimate the average minimum time-to-failure of a power grid under workload uncertainties. The results indicate that the series model, which is currently used in the industry, gives a pessimistic estimate of power grid MTF and reliability by a factor of 3-4. Finally, we exploit multithreading and grid locality to speedup our implementation by almost $6{\times }$ .

Electromigration (EM) is re-emerging as a significant problem in modern integrated circuits (IC). Especially in power grids, due to shrinking wire widths and increasing current densities, there is little or no margin left between the predicted EM stress and that allowed by the EM design rules. Statistical Electromigration Budgeting (SEB) estimates the reliability of the grid by considering it entirely as a series system. However, a power grid with its many parallel paths has much inherent redundancy. In this paper, we propose a new model to estimate the MTF and reliability of the power grid under the influence of EM, which accounts for these redundancies. We refer to this as the mesh model. To implement the mesh model, we also develop a framework to estimate the change in statistics of an interconnect as its effective-EM current varies. The proposed algorithm is quite fast and has an overall observed empirical complexity of 0(n1.4). The results indicate that the series model, which is currently used in the industry, gives a pessimistic estimate of power grid MTF and reliability by a factor of 3-4.

Electromigration (EM) in the on-die metal lines has re-emerged as a significant concern in modern VLSI circuits. The higher levels of temperature on die and the very large number of metal lines, coupled with the conservatism inherent in traditional EM checking strategies, have led to a situation where trying to guarantee EM reliability often leads to unacceptably conservative designs that may not meet the area or performance specs. Due to unidirectional currents, this problem is most significant in the power and ground grids. Thus, this work is aimed at reducing the pessimism in EM prediction for power/ground grids. There are two sources for the high pessimism: 1) the use of the traditional series model for EM checking and 2) pessimistic assumptions about the chip workload and the corresponding supply currents. To address this problem, we propose a framework for EM checking that allows users to specify conditions-of-use type constraints that help capture realistic chip workload and which includes the use of a novel mesh model for EM prediction in the grid, instead of the traditional series model.

Exceptions have traditionally been used to handle infrequently occurring and unpredictable events during normal program execution. Current trends in microprocessor and operating systems design continue to increase the cost of event handling. Because of the deep pipelines and wide out-of-order superscalar architectures of contemporary microprocessors, an event may need to nullify a large number of in-flight instructions. Large register files require existing software systems to save and restore a substantial amount of process state before executing an exception handler. At the same time, processors are executing in environments that supply higher event frequencies and demand higher performance. We have developed an alternative architecture, "concurrent event handling", that incorporates multithreading into event handling architectures. Instead of handling the event in the faulting thread's architectural and pipeline registers, the fault handler is forked into its own thread slot and executes concurrently with the faulting thread. Microbenchmark programs show a factor-of-3 speedup for concurrent event handling over a traditional architecture on code that takes frequent exceptions. We also demonstrate substantial speedups on two event-based applications. Concurrent event handling is implemented in the MIT's MAP (Multi-ALU Processor) chip.