This paper contributes to the field of MBIST architecture and implementation by addressing the two most area-critical components: the Command Memory (ComMem) and the Address Generator (AddrGen). The ComMem area is minimized by using a novel MBIST architecture, based on the Generic March Element (GME) concept. A GME is a March Element which specifies the required operations and the generic data values; it can be specified independent of the algorithm stresses. The AddrGen area is minimized by using an efficient implementation, based on a single Up-counter and a set of multiplexors. The experimental results show that the proposed MBIST outperforms the existing MBISTs in terms of area, power, speed, and flexibility. E.g., for a 16Kx16-bit memory, the proposed MBIST consumes about 40% less area and operates at least 1.6 times faster than the state-of-the art.

Many systems are based on embedded microcontrollers. Applications demand for production and Power-On testing, including memory testing. Because low-end microcontrollers may not have memory BIST, the CPU will be the only resource to perform at least the Power-On tests. This paper shows the problems, solutions and limitations of CPU-based at-speed memory testing, illustrated with examples from the ATMEL RISC microcontroller.

Small microcontroller-based systems are omnipresent. Often, they do not have Memory BIST (MBIST), or the MBIST is not available to the user. In such cases the CPU will be the only resource to perform at least the Power-On testing of the embedded memories. This paper highlights the capabilities and limitations of CISC architectures to apply at-speed memory tests.

This paper contributes to the field of test engineering: it shows the tradeoffs and engineering aspects of a low-cost, flexible SRAM MBIST engine, applied to the 768 and 256 byte SRAMs of an 8051 microcontroller. The simplicity and orthogonality of the architecture allowed for a full-custom implementation by Micronas in 120 hours of design time, while the area is reduced by 75% of an earlier commercial version.

Summary form only given: Embedded memories have become the fastest growing segment of Systems on Chip (SoC) in recent years. According to the International Technology Roadmap for Semiconductors, embedded memories will continue to dominate the increasing SoC chip area in the future, approaching 94% within one decade. Hence, these memories will severely impact all aspects of SoC manufacturing including yield, quality and reliability. Additionally, nanotechnology is causing higher levels of device-parameter variations and new failure mechanisms that are not yet well understood. Precise fault modeling to design efficient tests is therefore essential in order to keep the test cost and test time within economically acceptable limits, while keeping higher product quality. The objective of this embedded tutorial is to provide test engineers, memory and ASIC designers, researchers, students and managers with an overview of state-of-the art of fault models for SRAMs (including traditional fault modeling and recent development in fault models for current and future technologies), together with the latest test algorithms. Next, it describes test plans, which are shown to depend on the size of the SRAM, its speed, and the application domain. Thereafter, industrial results are used to show the effectiveness of the proposed algorithms and stresses. Last, future challenges in embedded memory testing (e.g., in fault modeling, test design) are highlighted.

Due to the rapid decrease of technology feature size speed related faults, such as Address Decoder Delay Faults (ADDFs), are becoming very important. In addition, increased leakage currents demand for improved tests for Bit Line Imbalance Faults (BLIFs)(caused by memory cell pass transistor leakage). This paper contributes to new and improved algorithms for detecting these faults. First it provides an improved version of existing GalPat algorithm and introduces two new algorithms to detect ADDFs; the paper also shines a new light on the use of the different stress combinations (counting methods, data-backgrounds) and their importance for the detection of ADDFs. Second, it provides an improved algorithm for detecting BLIFs; it increases the defect coverage by being able to detect lower leakage currents.

Efficient and effective methods are needed to generate defect oriented tests for todays VLSI circuits. This paper describes an industrial case study for using defect injection and Spice simulation to generate defect oriented tests for the so-called strap defects in DRAMs, taking both the sensitivity of this defect to process variations and bit line coupling into consideration. The paper discusses all the different stages of the test generation process, starting with defect modeling, followed by the simulation methodology, test generation and optimization, and finally test application and industrial evaluation performed in Qimonda. Results show that the generated tests have the same coverage as previously used tests with possible test time reduction of up to 59%. The analysis also identifies the slow process corner and the data backgrounds 11 and 01 as the most stressful combinations to test the strap. The paper also discusses a test method used to account for process variations and detect the fault in any process corner.

DRAMs play an important role in the semiconductor industry, due to their highly dense layout and their low price per bit. This paper presents the first framework of fault models specifically designed to describe the faulty behavior of DRAMs. The fault models in this paper are the outcome of a close collaboration with the industry, and are validated using a detailed. Spice-based analysis of the faulty behavior of real DRAMs. The resulting fault space is then used to derive a couple of new DRAM-specific tests, needed to detect some of the faults in practice

DRAM testing has always been theoretically considered as a subset of general memory testing, despite the disagreement of this assumption with the DRAM test practice. This paper presents a recently developed space of DRAM faults that describes the unique aspects of DRAM behavior, it validates this fault space using extensive Spice simulation, and it identifies the memory tests necessary to detect these faults. Six different tests are derived and shown to correspond to highly effective DRAM tests in practice

This paper presents a complete electrical analysis of address decoder delay faults "ADFs" caused by resistive opens in RAMs. A classification between inter and intragate opens is made. A systematic way is introduced to explore the space of possible tests to detect these faults; it is based on generating appropriate sensitizing address transitions and the corresponding sensitizing operation sequences. DFT features are given to facilitate the BIST implementation of the new tests

With the continued advances in miniaturization, bit-line (BL) coupling is becoming ever more influential on the memory behavior. This paper discusses the effects of BL coupling on the faulty behavior of defective dynamic RAMs. It starts with an analytical evaluation of coupling effects, followed by a simulation-based fault analysis using a Spice simulation model. Two BL coupling mechanisms are identified (pre-sense and post-sense coupling), which are found to have a partly opposing effect on the faulty behavior. It is shown that BL coupling causes a special kind of coupling fault between adjacent memory cells. In addition, the influence of BL twisting on the faulty behavior of the memory is analyzed and simulated. The results indicate strong correspondence between theory and simulation and show the importance of Spice simulation as a vital tool for fault analysis

With the increasing complexity of memory behavior, attempts are being made to come up with a methodical approach that employs electrical simulation to tackle the memory test problem. This paper describes a framework of algorithms and tools developed jointly by the Delft University of Technology and Infineon Technologies to systematically generate DRAM tests using Spice simulation. The proposed Spice-based test approach enjoys the advantage of being relatively inexpensive, yet highly accurate in describing the desired memory faulty behavior.

Memory testing in general, and DRAM testing in particular, has become greatly dependent on the modification of stresses (timing, temperature and voltages) in a way that is difficult to justify using the current understanding of memory faults. This paper introduces a new class of fault models (soft faults) based on a special classification of memory faults, that shows why it is fundamentally necessary to apply stresses. The paper calculates the relative probability of soft faults for a specific failure mechanism and compares this probability in DRAMs with that in SRAMs. In addition, the concept of soft faults is validated using defect injection and electrical simulation of a Spice DRAM model.

This paper presents an electrical analysis of Address decoder Delay Faults 'AFDs' caused by resistive inter-gate opens in RAMs. It introduces a systematic method to explore the space of possible tests to detect these faults. The method is based on generating appropriate sensitizing address transitions and the corresponding sensitizing operation sequences.

Very little has been published on faults in the memory peripheral circuits, denoted as 'PFs'. This work shows that PFs are detected by March tests, provided that they satisfy particular properties, expressed in terms of properties of the algorithm, and of properties of the algorithm stress. The latter consists of the used data backgrounds and addressing directions. The detection capabilities of a set of well-known March algorithms are established for the PFs. In addition, industrial results from applying this set of tests to a large number of 0.13 micron 512 Kbyte SRAM chips, combined with a variety of stress conditions, are presented.

With the shrinking dimensions of manufactured structures on memory chips and the increase in memory size, bit line coupling is becoming ever more influential on the memory behavior. This paper discusses the effects of bit line coupling on the faulty behavior of DRAMs. It starts with an analytical evaluation of coupling effects, followed by a simulation-based fault analysis using a SPICE simulation model. Two bit line coupling mechanisms are identified, pre-sense and post-sense coupling, and found to have a partly opposing effect on the faulty behavior. In addition, the impact of neighboring cells on these coupling mechanisms is investigated.

The analysis of linked faults (LFs), which are faults that influence the behavior of each other, such that masking can occur, has proven to be a source for new memory tests, characterized by an increased fault coverage. However, many newly reported fault models have not been investigated from the point-of-view of LFs. This paper presents a complete analysis of LFs, based on the concept of fault primitives, such that the whole space of LFs is investigated and accounted for and validated. Some simulated defective circuits, showing linked-fault behavior, will be also presented. The paper establishes detection conditions along with new tests to detect each fault class. The tests are merged into a single test March SL detecting all considered LFs. Preliminary test results, based on Intel advanced caches, show that its fault coverage is high as compared with all other traditional tests and that it detects some unique faults; this makes March SL very attractive industrially.

As a result of variations in the fabrication process, different memory components are produced with different operational characteristics, a situation that complicates the fault analysis process of manufactured memories. This paper discusses the issue of process variations, and shows how to deal with it in the context of fault analysis and test generation. The paper also introduces the concept of border resistance traces as a tool to optimize test stresses and inspect the impact of process variations on the optimization procedure. The concepts are discussed in the paper with the help of a practical example of a specific defect in the memory.

The analysis of linked faults has proven to be a source for new memory tests, characterized by an increased fault coverage. The paper gives a set of five new tests to target all possible linked faults. The tests are merged into a single test, March SL, detecting all faults in the linked fault space. The preliminary test results of an experiment done at Intel are reported; they show that March SL scores high and detects some unique faults.

This paper improves upon the state of the art in testing word oriented memories. It first presents a complete set of fault models for intra-word coupling faults. Then, it establishes the data background sequence (DBS) for each intra-word coupling fault. These DBSs will be compiled into a (1 + 28 * [log/sub 2/B]) * n/B test with complete fault coverage of the target faults, where n is the size of the memory and B the word size. The test length can be reduced to 29 * n/B when the intra-word faults are restricted to physical adjacent cells within a word.

Spot defects in memory devices are caused by imperfections in the fabrication process of these devices. In order to analyze the faulty effect of spot defects on the memory behavior, simulations have been performed on an electrical model of the memory in which the defects are injected, causing opens, shorts, or bridges. In this paper, simulation is used to analyze the faulty behavior of embedded DRAM (eDRAM) devices produced by Infineon Technologies. The paper applies the new approach of fault primitives to perform this analysis. The analysis shows the existence of most traditional memory fault models and establishes new ones. The paper also investigates the concept of dynamic faulty behavior and establishes its importance for eDRAMs. Conditions to test the newly established fault models, together with a test, are also given.

Most memory test algorithms are optimized for a particular memory technology and a particular set of fault models, under the assumption that the memory is bit-oriented, i.e., read and write operations affect only a single bit in the memory. Traditionally, word-oriented memories have been tested by repeated application of a test for bit-oriented memories, whereby a different data background is used during each application. This results in time inefficiencies and limited fault coverage. A systematic way of converting tests for bit-oriented memories into tests for word-oriented memories is presented, distinguishing between interword and intraword faults. The conversion consists of concatenating to the test for interword faults, a test for intraword faults. This approach results in more efficient tests with complete coverage of the targeted faults. Word-oriented memory tests are very important, because most memories have an external data path which is wider than one bit.

Although electrical simulation has become a vital tool in the design process of memory devices, memory testing has not yet been able to employ electrical simulation as an integral part of the test generation and optimization process. This is due to the exponential complexity of the simulation-based fault analysis, a complexity that made such an analysis impractical. This paper describes new methods to reduce the complexity of the fault analysis from exponential to constant with respect to the number of analyzed operations, thereby making it possible: 1) to use electrical simulation to generate test patterns; and 2) to perform simulation-based stress optimization of tests. The paper also discusses ways to analyze the impact of idle time on the faulty behavior. In addition, results of a fault analysis study performed to verify the new analysis method are shown, where the new analysis reduces the analysis time by a factor of 30.

To limit the exponential complexity required to analyze the dynamic faulty behavior of DRAMs, algorithms have been published to approximate the faulty behavior of DRAM cell defects. These algorithms, however, have limited practical application since they are based on generic memory operations (writes and reads) rather than the DRAM specific operations (activation, precharge, etc.). This paper extends the approximation algorithms by incorporating the DRAM specific operations, making them directly applicable in practice. In addition, based on the new extended method, the paper shows results of a fault analysis study of cell defects using electrical simulation.

It has always been assumed that fault models in memories are sufficiently precise for specifying the faulty behavior This means that, given a fault model, it should be possible to construct a test that ensures detecting the modeled fault. This paper shows that some faults, called partial faults, are particularly difficult to detect. For these faults, more operations are required to complete their fault effect and to ensure detection. The paper also presents fault analysis results, based on defect injection and simulation, where partial faults have been observed. The impact of partial faults on testing is discussed and a test to detect these partial faults is given.

Most industrial memories have an external word-width of more than one bit. However, most published memory test algorithms assume 1-bit memories; they will not detect coupling faults between the cells of a word. This paper improves upon the state of the art in testing word-oriented memories by presenting a new method for detecting state coupling faults between cells of the same word, based on the use of m-out-of-n codes. The result is a reduction in test time, which varies between 26 and 38%.

Efficient production testing is frequently hampered because current digital circuits require test sets which are too large. These test sets can be reduced significantly by means of test point insertion (TPI). The state-of-the-art TPI methods only focus on solving one or two possible testability problems, and sometimes even fail to result in test set size reduction because they focus on the wrong testability problem. In this paper, we propose two TPI pre-process methods that analyze the circuit and select the TPI method that will focus on the testability problems that really exist. Experimental results indicate that with these pre-processes, better test set size reductions can be achieved. Gate-delay fault ATPG test sets tend to be even larger than stuck-at fault ATPG test sets. In this paper we have evaluated the impact of TPI on gate-delay fault test sets. Experimental results indicate that TPI also results in a significant test set size reduction for gate-delay fault ATPG.

Analyzing the dynamic faulty behavior in DRAMs is a severely time consuming task, because of the exponential growth of the analysis time needed with each memory operation added to the sensitizing operation sequence of the fault. In this paper, a new fault analysis approach for DRAM cell defects is presented where the total infinite space of dynamic faulty behavior can be approximated within a limited amount of analysis time. The paper also presents the analysis results for some cell defects using the new approach, in combination with detection conditions that guarantee the detection of any detectable dynamic faults in the defective cell.

The ever increasing trend to reduce DPM levels of memories requires tests with very high fault coverage. The important class of dynamic faults, therefore, cannot be ignored any more. It is shown that conventional memory tests constructed to detect static faulty behavior of a specific defect do not necessarily detect the dynamic faulty behavior. Indeed, dynamic faulty behavior can take place in the absence of static faults. The paper presents new memory tests derived to target the dynamic fault class.

This paper begins with an overview of realistic fault models for dual-port memories, divided into single-port faults and faults unique for dual-port memories. The latter faults cannot be detected with conventional single-port memory tests; they require special tests. A precise notation for all faults, such that ambiguities and misunderstandings are prevented, has been emphasized. Next, the paper presents a methodology to design tests for realistic unique dual-port memory faults, resulting in a set of three linear single-addressing tests which are merged into a single march test (March s2PF), and one linear double-addressing test (March d2PF). March s2PF and March d2PF have been implemented at Intel. The results show that they detect unique faults, i.e., faults that cannot be detected with conventional single-port memory tests. This make them very attractive industrially.

The quality of tests, in terms of fault coverage and test length, is strongly dependent on the used fault models. This paper presents realistic fault models for multiport memories with p ports, based on defect injection and SPICE simulation. The results show that the fault models for p-port memories consist of p classes: single-port faults, two-port faults, ..., p-port faults. In addition, the paper discusses the test procedure for such memories; it shows that the time complexity of the required tests is not exponential proportionally with p, as published by different authors, but it is linear, irrespective of the number of ports of which the multiport memory consists.

This paper shows the shortcomings of the current, generic notation for fault models and extends it to allow the description of fault models for DRAMs. The advantage is that the extended fault models can easily be translated into operation sequences and tests that detect the described fault. Examples are given to show that the new notation results in optimized, memory specific, tests that have a shorter run time for a given fault coverage.

Short transparent memory test algorithms for semiconductor memories are presented along with an evaluation of the space on silicon required for their built-in self-test implementation. A modified version of the memory test simulation package MAP+ has been developed and employed for test algorithms generation and simulation.

This paper begins with a brief overview of realistic fault models for multi-port SRAMs with p ports, divided into p classes: single-port faults, two-port faults,..., p-port faults. Except for single-port faults, all other fault classes cannot be detected with the conventional (single-port) memory tests; they require special tests. Next, the paper presents a set of three linear single-addressing tests for unique multi-port memory faults (p > 2) that will be merged into a single test.

Presents a complete analysis, at the electrical level, of address decoder faults caused by resistive opens, and by capacitive-coupling between address lines. Several authors have demonstrated the importance of this class of faults. New test conditions, and new march tests are derived to detect the resulting faults; and industrial results, applied to DRAMS, show the effectiveness of the new tests.

Fault analysis of memory devices using defect injection and simulation is becoming increasingly important as the complexity of memory faulty behavior increases. In this paper this approach is used to study the effects of opens and shorts on the faulty behavior of embedded DRAM (eDRAM) devices produced by Infineon Technologies. The analysis shows the existence of previously defined memory fault models, and establishes new ones. The paper also investigates the concept of dynamic faulty behavior and establishes its importance for memory devices. Conditions to test the newly established fault models are also given.

Temperature has proven to be an effective stress condition, commonly used to stress memory devices and to detect special types of failure mechanisms. In this paper a new approach is presented where temperature is used as a test parameter to increase the fault coverage of specific tests. This is done using defect injection and simulation of a memory model at different temperatures. The analysis presents new types of detection conditions for memories and evaluates the impact of temperature on these conditions.

Establishing functional faults, based on defect injection and circuit simulation, has become an important method in understanding faulty memory behavior and in improving memory tests. In this paper this approach is used to study the effects of bridges on the faulty behavior of embedded DRAM (eDRAM) devices. The paper applies the new approach of fault primitives to perform this analysis. The analysis shows the existence of previously defined memory fault models, and (re)establishes new ones. The paper also investigates the concept of dynamic faulty behavior and establishes its importance for memory devices.

In this paper a complete analysis of spot defects in industrial SRAMs will be presented. All possible defects are simulated, and the resulting electrical faults are transformed into functional fault models. The existence of the usually used theoretical memory fault models will be verified and new ones will be presented. Finally, a new march test detecting all realistic faults, with a test length of 14n, will be introduced, and its fault coverage is compared with other known tests.

Efficient production testing is frequently hampered because (cores in) current complex digital circuit designs require too large test sets, even with powerful ATPG tools that generate compact test sets. Built-in Self-Test approaches often suffer from fault coverage problems, due to random-resistant faults, which can be improved successfully by means of Test Point Insertion (TPI). In this paper, we evaluate the effect of TPI for BIST on the compactness of ATPG generated test sets and it turns out that most often a significant test set size reduction can be obtained. We also propose a novel TPI method, specifically aimed at facilitating compact test generation, based on the ''test counting' technique. Experimental results indicate that the proposed method results in even larger and moreover more consistent reduction of test set sizes.

This paper describes the results of testing 50 single inline memory modules (SIMMs) each containing 16 16 Mbit DRAM chips (DUTs); 39 SIMMs failed, and of the 800 DUTs, 116 failed. In total 54 different test algorithms have been applied, using up to 168 different stress combinations for each test. The results show that GAL9R is the best test. Furthermore, it is shown that burst mode tests detect a completely different class of faults as compared with traditional word mode tests, and that tests with address scrambling enabled the detection of more faults.

This paper presents a notation for describing functional fault models, which may occur in memory devices. Using this notation, the space of all possible memory faults has been constructed. It has been shown that this space is infinite, and contains the currently established fault models. New fault models in this space have been identified and verified using resistive and capacitive defect injection and simulation of a DRAM model.

This paper presents a structured way of deriving new functional fault models, based on the insertion of resistive defects into the electrical schematic of an SRAM. A taxonomy of the set of possible electrical faults is given, a set of primitive patterns to drive the electrical level simulator is derived, the existing notation for functional faults is revisited, and simulation results prove the existence of new functional faults.

This paper presents an approach for testing word-oriented multi-port memories. Fault models for such memories are given based on fault models for bit-oriented multi-port memories. A distinction between intra-word faults and inter-word faults as made. A systematic way of converting bit-oriented multi-port memory tests into word-oriented multi-port memory tests is presented.

The search for tests for sequential circuits (STPG) by deterministic test pattern generation is a process of alternately performing mandatory assignments and heuristic decisions on signal lines. We have observed problems in the decision-making process due to shortcomings in the SCOAP controllability/observability metrics and the backtrack process during STPG. In this paper we propose new techniques to improve the controllability/observability metrics, and two forms of conflict-directed backtracking (back-jumping) to improve the backtrack process. Experimental results demonstrate that the proposed techniques are very promising and result in a significant improvement in fault efficiencies and CPU usage for the ISCAS'89 and industrial circuits.

This paper presents the results of 44 well known memory tests applied to 1896 1M*4 DRAM chips, using up to 96 different stress combinations with each test. The results show the importance of selecting the right stress combination, and that the theoretically better tests (i.e. those covering different functional faults) also have a higher fault coverage. However the currently used fault models still leave much to be explained; e.g., the used data backgrounds and address orders show an unexplainable large variation in fault coverage.

Here our new techniques are proposed to expand the known Global Illegal State (GIS) space, in order to reduce the search space. These techniques use the known GISes to generate candidate GISes, which have to be proven unjustifiable. This is an effective method to improve STPG performance because the number of stored GISes is reduced, saving memory and CPU time, while covering a larger part of the GIS space. To accelerate GIS space identification, we propose the legal state cache, to avoid useless justification repetitions. A data-structure is proposed to reduce the memory usage of the (G)ISes up to 10 times, and to accelerate GIS usage. Experimental results show a significant improvement in fault efficiency and CPU usage.

This paper presents the results of ten well-known memory test algorithms and four memory test primitives applied to 3876 256 Kbit SRAM chips, using 128 different stress combinations with each test algorithm. The results show that stress combinations influence the coverage of the test algorithms for these SRAMs, and that the influence is less for these SRAMs than for DRAMs. Selecting the right stress combination allows for using a simpler algorithm. The simple memory test primitives can detect all faults given the proper stresses. Power supply voltage turns out to be a very important non-algorithmic stress.

A two-port memory contains two similar ports, which can be accessed separately and independent of each other. In this paper, logical fault models are derived for the effect of shorts between the ports. The result is a set of new fault models, based on circuit simulation, together with a new test.

This paper presents the research results of the sequential testability of the Philips 80C51 microcontroller. The motivations for this research were to save chip area and test application time (i.e., reducing the production costs), and to evaluate the effectiveness and efficiency of the Delft Automatic Test (DAT) generation system for sequential circuits on real industrial sequential circuits, such as the 80C51. ATPG has been performed on a fully sequential version (non-scan), and on several partial-scan versions of the 80C51. The stuck-at fault coverage of the full-scan version is above 91%, while the fault coverage of the non-scan version is almost zero. Therefore, partial-scan versions of the 80C51 have been developed to achieve the fault coverage level of the full-scan version. Experimental results demonstrate that almost 50% of the FFs have to be scannable in order to approach the fault coverage of the full-scan version. The fault coverage is reduced by /spl plusmn/10%, when /spl plusmn/30% of the FFs have been selected for scan.

Summary BIST may be the best way for testing embedded memories; however, for small embedded memories, functional tests (e.g., performed by a processor’s microcode or applied via a scan path) may be a more cost-effective solution. The reason is that signal levels in smaller memories are relatively strong such that faults induced by noise, etc., which are hard to detect, are less likely to occur. The concern for BIST for embedded DRAMS is that fault localization may be required: this can be taken care of easily however. Additionally, the effectiveness of tests has been shown to be heavily dependent on stress conditions such as timing, temperature (leakage is exponentially proportional with temperature), and voltage. Some of these stress conditions are hard to apply in a BIST environment (except perhaps at the wafer level), such that BIST is also required at the wafer and/or chip level, or else alternative tests have to be used instead. Iddq testing has not shown to be very effective for SRAMs, because many faults cause a state change in the cell or only occur during a read/write operation (which is too short for Iddq measurement), and is ineffective for DRXMs because of the small signal and charge levels. Iddq is not able to replace burn-in because it is not an effective test for memories and is therefore also a poor reliability predictor.

Testing two-port memories requires the use of single-port tests as well as special two-port tests; the test strategy determines which tests have to be used. Many two-port memories have ports which are read-only or write-only; this impacts the possible tests for single-port and two-port memories, as well as the test strategy. This paper discusses the consequences of the port restrictions (read-only or write-only ports) on the tests; in addition it covers the test strategy for address decoder faults in two-port memories.

Test Pattern Generation (TPG) for sequential and/or 3-state circuits involves two important aspects which often are handled incorrectly: bus conflict detection and completeness of search in TPG. The correct handling of both aspects strongly depends on the signal model used by TPG. We propose a novel, set-based, signal model using the power-set (i.e., the set of all possible subsets) of the basic values {0, 1, Z}. TPG using this signal model guarantees complete search, provides exact bus-conflict detection, and is more efficient than TPG using the traditional signal models for J-state and sequential circuits. Experimental results demonstrate this by higher fault efficiencies combined with a large reduction of backtracking and computing time for sequential ISCAS'89 and industrial circuits.

Most memory test algorithms are optimized tests for a particular memory technology, and a particular set of fault models, under the assumption that the memory is bit-oriented; i.e., read and write operations affect only a single bit in the memory. Traditionally, word-oriented memories have been tested by repeated application of a test for bit-oriented memories whereby a different data background (which depends on the used intra-word fault model) is used during each iteration. This results in rime inefficiencies and limited fault coverage. A new approach for testing word-oriented memories is presented, distinguishing between inter-word and intra-word faults and allowing for a systematic way of converting tests for bit-oriented memories to rests for word-oriented memories. The conversion consists of concatenating the bit-oriented test for inter-word faults with a test for intra-word faults. This approach results in more efficient tests with complete coverage of the targeted faults. Because most memories have an external data path which is wider than one bit, word-oriented memory tests are very important.

Testing two-port memories requires the use of single-port tests as well as special two-port tests; the test strategy determines which tests to be used. Many two-port memories have ports which are read-only or write-only; this impacts the possible fault models, the tests for single-port and two-port memories, as well as the test strategy. This paper presents a test strategy for two-port memories and covers the consequences of the port restrictions (read-only or write-only ports).

Memories are often used as a semiconductor manufacturing process monitoring vehicle. This paper describes a new memory built-in self-test (BIST) method that is used to monitor the semiconductor manufacturing process. For this purpose, this BIST method has the ability not only to generate a pass/fail verdict for the tested memory, but also to report additional information to be able to narrow down the type and the location of the failure mode that is causing the tested memory to fail. Also, it offers test algorithm flexibility. The described BIST method has successfully been implemented in a dedicated process monitoring chip that is now being used in large quantities.

In this paper the effects of simultaneous memory access on the fault modeling for two-port memories are investigated. New fault models and their march tests are presented. The obtained tests are of order O(n/sup 2/), which makes them less practical for larger two-port memories. However, the complexity can be reduced to O(n), when the memory topology is taken into account.

The increasing emphasis on reducing the defect level of shipped memory parts demands very high fault coverage of memory tests. Deterministic tests have the advantage of 100% fault coverage for the targeted (i.e., anticipated) faults. However, with each new technology, new layout and new fab process, new types of defects will show up; the probability of occurrence of these defects is not known before production start and, in addition, may vary during the time period the parts are produced. Pseudo-random (PR) memory tests are tests which have the capability to detect any fault (defect) of any model; albeit with some probability less than 100%; the fault coverage is modular and depends on the test time, which makes them very attractive. However, problems arise when commercial testers have to be used for applying PR tests. This paper illustrates these problems and shows how they can be overcome. The results are applicable to a large class of commercial memory testers thereby making them useable for PR memory tests.

TPG for synchronous sequential circuits has received wide attention over the last two decades, yet unlike for (full-scan) combinational circuits, for many sequential benchmark circuits 100% fault efficiency still cannot be reached. This illustrates the complexity of sequential circuit ATPG. The huge search space, which exists during sequential circuit TPG, is the main reason for this complexity. Powerful techniques and heuristics are required to cope with this search space. One way to reduce the search space is the detection of illegal states. These states cannot be justified with an initialization sequence. In this paper, we propose new techniques to find illegal states and to remove the over-specification of these states by searching common fractions in the list of illegal states. Experimental results demonstrate the importance of an as complete as possible illegal state list: Higher fault efficiencies are reached for the sequential ISCAS'89 circuits (1989) and industrial circuits, together with a large reduction of CPU time.

With the increase in memory density, neighborhood pattern sensitive faults (NPSFs) are not only an important fault model for DRAMs but will also become so for SRAMs. NPSFs can be considered generalized versions of simple-cell faults and two-cell coupling faults, whereby the extra cells involved in the NPSF are required to have an enabling value. A new coupling fault model, the disturb fault (CFdst) has been published (van de Goor 1996). It has the property that it is more consistent with the true behavior of the memory, while tests for CFdsts can be designed such that they also cover idempotent CFs. It is the purpose of this paper to extend the concept of CFdsts to NPSFs based on CFdsts (i.e. the Disturb NPSFs) and present tests for those DNPSFs. It will be shown that the tests for DNPSFs are more efficient than those of the traditional tests for NPSFs while they also cover the faults of the traditional NPSFs.

The problem of designing memory tests is to establish a relevant set of fault models only consisting of those faults which are shown to be possible to occur in practice. Thereafter, it is a challenge to the test designer to design an optimum test covering the faults of the established fault models. A new fault model, the disturb fault model, is introduced. The notation of linked faults is established and it is shown that march tests can only detect a subset of all linked faults. Thereafter, the universe of linked faults is reduced to the set of realistic linked faults. Last, the effectiveness of the realistic linked fault model is shown via new tests with a higher fault coverage and a shorter test length.

Circuit partitioned approaches to ATPG have been developed and used over the last two decades, depending on the ratio between state-of-the-art in ATPG and circuit sizes. A practical form consists of coarse-grain, cone-oriented partitioning of the circuit. We investigated the problems introduced by practical ATPG constraints: keeping tests (3-state) bus-conflict free, and complying to external restrictions and exclusions on test patterns. A cone-oriented circuit partitioning method dealing with these problems is proposed. A serial ATPG scheme for the partitions is proposed. The combined effectiveness is shown by experimental results.

Most published ATPG methods cannot handle three-state primitives, generate too large test sets, or require excessive CPU time. An efficient ATPG system was introduced by M.H. Konijnenburg et al. (1995) and J.Th. van der Linden et al. (1994), which can handle non-Boolean primitives, generates compact test sets, within affordable CPU time. In this paper, the system is extended to handle pulled and wired buses, in addition to pure three-state buses. These bus types are widely used in industrial circuits. Furthermore five techniques for test generation are proposed to accelerate (compact) ATPG. Experimental results demonstrate that these new techniques are useful: ATPG times for compact test set generation are decreased up to 50% compared to that reported previously by Konijnenburg et al. and fault efficiencies above 99% can be obtained for even the largest circuits.

Many march tests have already been designed to cover faults of different fault models. The complexity of these tests arises when linked faults are taken into consideration. This paper gives an overview of the most important and commonly used fault models, including the industry's popular disturb fault model. The fault coverage of march tests is analysed in a novel way, i.e., in terms of their detection capabilities for: simple faults, and linked faults; whereby the infinite class of linked faults has been reduced to a set of realistic linked faults. Thereafter the paper presents a methodology to design tests for realistic linked faults, resulting in the new tests March LR, March LRD and March LRDD. These new tests will be shown to be more efficient and to offer a higher fault coverage than comparable existing tests.

To be able to manage increasing chip complexity, the re-use of already designed functional modules has become a standard design practise in state-of-the-art ASIC design. In this paper, the impact of these re-used modules on the testability of the entire chip has been investigated. For this purpose, a complex telecom ASIC with re-used interface logic running at 155 MHz, used in an ATM (Asynchronous Transfer Mode) application, has been studied. The single stuck-at fault coverage for the random logic, obtained with combinational ATPG, has been increased by 21% by performing some minor design modifications and using sequential ATPG. In addition, it has been shown that with respect to I/sub DDQ/ testing, automatic test vector generation has to be preferred over fault grading hand-written functional test vector sets. With I/sub DDQ/ test vector generation 95% fault coverage has been obtained with only 66% of the flip-flops being scannable.

Industrial circuits contain, in addition to the binary logic elements [n] and, [n] or and [n] xor gates, other logic elements such as three-state elements, busses and bidirectionals. Previous published work on automatic test pattern generation (ATPG) can not handle all of the above mentioned circuit elements, generates too large test sets, or generates test patterns which can cause circuit damage. A new fast ATPG system for industrial circuits is introduced capable of coping with all of the above mentioned circuit elements, will not cause circuit damage and generates compact test sets using new heuristics for compaction oriented decision making. Experimental results show that the compact test sets are much smaller than in [vdL94b] (on average 60%). The extra ATPG time required for generating these compact test sets is a relatively small penalty compared to the decrease in test set size.

A 16/spl times/16-bit wave-pipelined multiplier was designed using static CMOS. Wave pipelining is achieved by applying new data to the circuit faster than the propagation delay. The circuit has been fabricated in a 1.0 /spl mu/m CMOS process and tested at 330-350 MHz, which is about 4 times faster than the maximum clock frequency without pipelining.>

Many memory tests have been designed in the past, one class of tests which has been proven to be very efficient in terms of fault coverage as well as test time, is the class of march tests. Designing march tests is a tedious, manual task. This paper presents a method which can, given a set of fault models, automatically generate the required march tests. It has been implemented in the programming language C and shown to be effective.

Industrial circuit designs commonly contain three-state elements, such as buses and drivers, transmission gates, and bidirectional I/O. A 5-valued fast fault simulation method and a 4-valued parallel pattern version that can handle these circuits are presented. Results demonstrate the effectiveness of the proposed methods in the presence of three-state elements, and show but a small performance degradation compared to 2- or 3-valued fault simulation.

FIFO memories impose special test problems because of their built-in addressing restrictions and access limitations. With the increasing usage of FIFOs today, generic algorithms are needed to test stand-alone FIFO chips and embedded FIFO macros. This paper addresses the problem of testing a very popular type of FIFO, namely the ring-address FIFO. It introduces two novel algorithms to test this type of FIFO. Both algorithms provide full fault coverage for a comprehensive fault model. The first algorithm uses a generic test approach in the sense that it does not require any change to the FIFO hardware. Whereas, the second algorithm is DFT-based. It assumes access to a FIFO design and suggests minor DFT modifications, in order to reduce the test complexity from O(n/sup 2/) to O(n). The BIST architecture of the DFT-based algorithm, which has recently been utilized in different products, is also described.

Verification, consisting of completeness and irredundancy proofs for memory tests, can be quite complicated. This paper presents a method to automatically verify march tests for any type of fault. This method can be adapted for any other (non march) memory test. It presents a way of, mathematically, modeling faults and describes how the verification process has been automated.>

First-in First-Out memories are becoming increasingly popular as buffer storage between subsystems operating at different data rates. One common way to implement a FIFO is to use a dual-port SRAM memory with a ring-address mechanism consisting of an n-bit shift register (n is the number of words in the FIFO). This saves the address decoder circuitry and allows for higher speed operation, which makes this type of FIFO very popular, especially for embedded applications. The well known functional tests for SRAMs can not be applied to FIFOs because of their built-in access restrictions. Functional fault models and functional tests for Ring-Address Type FIFOs have not been studied and reported before; this paper aims at filling in this gap. It introduces functional fault models and presents a set of tests for Ring-Address Type FIFOs.>

Published work on stuck-at-fault test generation nearly exclusively considers circuits composed of only binary logic gates. Industrial designs commonly contain three-state elements, such as: buses and drivers, transmission gates, and bidirectional I/O. This paper presents extensions to state-of-the-art ATPG algorithms in order to handle these elements. A 25-valued signal model is used for test generation. Results demonstrate the effectiveness of the proposed extensions in the presence of various three-state elements, and show but a small performance degradation compared to the traditional 9-valued signal model for binary logic circuits.>

This paper extends state-of-the-art ATPG systems by including constraints, called restrictors, on the allowable values of the bits of a test vector. Such restrictors often occur in "real-world" circuits where certain bit positions of a test vector have to take on a particular value (e.g. in case of a reset line) or are prohibited from taking on a particular value (e.g. in order to prevent an illegal state to be entered). This paper describes the types of restrictors, as encountered in "real world" circuits; it shows the required modifications to ATPG algorithms for stuck-at faults in combinational circuits, in order to cope with restrictors; and finally, the results of experiments determining the consequences for the ATPG time and fault coverage are given. The overall conclusion is: restrictors can easily be implemented in any ATPG system; the use of restrictors is essential in "real-world" circuits; the influence of restrictors on the ATPG time is small while a new class of "redundant faults" is identified, belonging to that part of the circuit which cannot be tested due to the specified restrictors.>

In the early 1980's a method has been developed for functional testing of microprocessors (1-31. Current microprocessors have a functionul- ity, such as on-chip caches, which is not covered by the model of (I-31. This paper extends that functional model and proposes fault models togeth- er with tests for such microprocessors. The pro- posed concepts and algorithms have been applied to the i860 and show to be very effective, since faults were found which where not found by tradi- tional functional tests.

An approach is presented for the synthesis of 100% testable logic networks based on a test pattern generation system for the identification of redundant faults. A redundancy removal procedure for the elimination of redundant nodes and gates from the network is also presented. Elimination of redundancy is an important task in a logic synthesis system that aims at the synthesis of 100% testable logic networks. Logic synthesis algorithms tend to generate a large number of redundancies, most of which can be easily identified, but some of these redundancies are very hard to identify by logic minimization procedures as well as by conventional test pattern generation algorithms.>

A memory array is considered a collection of RAM chips interconnected via data lines, row-select lines and wordselect lines. The stuck-at and bridging fault models are assumed for those lines. For each type of line an algorithm to locate the fault, in the presence of possible faults in thle other lines and possible faults in the RAM chips, is presented. The algorithms are proven to be correct and an analysis of their robustness (insensitivity to other faults in the imemory anay) is given. The sequence in which the tests have to be performed is determined. Index Terms .. RAM testing, board testing, bridging faults, fault location.

The algorithm for detecting pattern-sensitive faults in memories, as presented by K.K. Salnja, K. Kinoshita (ibid., vol.34, no.3, p.284-7, 1985), is simplified. In addition, a new algorithm is presented which has a near optimal WRITE sequence.>

The control unit maps a semicontinuous address space of the computer into a segmented BCD-addressed address space of the disk. An interesting buffering system provides for the maximum memory access time of the PDP-8 and high disk transfer rate. In principle, the buffering could be generalized to handle arbitrarily long waiting delays. The position of the disk may be read under program control. The execution of erroneous command sequences are not permitted (and hardware detected). Out-of-range disk addresses are detected.

TSS/8 is an existence proof for a small-scale time-sharing system. Design, development, and performance analysis have occurred in quasiparallel. Performance analysis includes two models and two levels of simulation (using SIMULA). The final simulation, an accurate model of the real operating system, predicts the observed behavior.