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Maxim Kalaev

dblp:06/6787 · DBLP profile ↗
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3ranked-venue papers
2as first author
0since 2021 · last 2008
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Applied, interdisciplinary, general and emerging computing · 2 · 2 first-authorSystems, architecture and hardware · 1Software engineering, systems software and programming languages · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Interdisciplinary, comprehensive, and emerging computing
2 papers
Bioinformatics and computational biology · 100%
Computer architecture, parallel and distributed computing, and storage systems
1 paper
Processor architecture and microarchitecture · 100%

Topics — the 7 heaviest of 8, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Bioinformatics and computational biology
comparative genomics
0.112008
NetworkBLAST: comparative analysis of protein networks · Bioinform. 2008
Bioinformatics and computational biology › biological network
network biology
0.112008
Fast and Accurate Alignment of Multiple Protein Networks · RECOMB 2008
Bioinformatics and computational biology › biological network › network biology
protein complex identification
0.112008
NetworkBLAST: comparative analysis of protein networks · Bioinform. 2008
Bioinformatics and computational biology › protein analysis › protein-protein interaction › protein-protein interaction network analysis
protein interaction network alignment
0.112008
Fast and Accurate Alignment of Multiple Protein Networks · RECOMB 2008
Bioinformatics and computational biology › protein analysis › protein-protein interaction
protein-protein interaction network
0.112008
NetworkBLAST: comparative analysis of protein networks · Bioinform. 2008
Processor architecture and microarchitecture
front-end
0.012000
Early load address resolution via register tracking · ISCA 2000
Processor architecture and microarchitecture
pipelining
0.012000
Early load address resolution via register tracking · ISCA 2000

Methods — techniques the papers use, named apart from their topics

network alignment · 0.1
YearPublicationVenuePosition
2008 Fast and Accurate Alignment of Multiple Protein Networks
Maxim Kalaev, Vineet Bafna, Roded Sharan
RECOMB1
2008 NetworkBLAST: comparative analysis of protein networks
abstract
UNLABELLED: The identification of protein complexes is a fundamental challenge in interpreting protein-protein interaction data. Cross-species analysis allows coping with the high levels of noise that are typical to these data. The NetworkBLAST web-server provides a platform for identifying protein complexes in protein-protein interaction networks. It can analyze a single network or two networks from different species. In the latter case, NetworkBLAST outputs a set of putative complexes that are evolutionarily conserved across the two networks. AVAILABILITY: NetworkBLAST is available as web-server at: www.cs.tau.ac.il/~roded/networkblast.htm.
Maxim Kalaev, Michael E. Smoot, Trey Ideker, Roded Sharan
Bioinform.1
2000 Early load address resolution via register tracking
abstract
Higher microprocessor frequencies accentuate the performance cost of memory accesses. This is especially noticeable in the Intel's IA32 architecture where lack of registers results in increased number of memory accesses. This paper presents novel, non-speculative technique that partially hides the increasing load-to-use latency, by allowing the early issue of load instructions. Early load address resolution relies on register tracking to safely compute the addresses of memory references in the front-end part of the processor pipeline. Register tracking may be performed in any pipeline stage following instruction decode and prior to execution. Several tracking schemes are proposed in this paper: Stack pointer tracking allows safe early resolution of stack references by keeping track of the value of the ESP register (the stack pointer). About 25% of all loads are stack loads and 95% of these lends may be resolved in the front-end. Absolute address tracking allows the early resolution of constant-address loads. Displacement-based tracking tackles all loads with addresses of the form reg+immediate by tracking the values of all general-purpose registers. This class corresponds to 82% of all loads, and about 65% of these loads can be safely resolved in the front-end pipeline. The paper describes the tracking schemes, analyzes their performance potential in a deeply pipelined processor and discusses the integration of tracking with memory disambiguation.
Michael Bekerman, Adi Yoaz, Freddy Gabbay, Stéphan Jourdan, Maxim Kalaev, Ronny Ronen
ISCA5