Neural Architecture Search (NAS) automates the design of deep neural networks (DNNs), but the design of the search space remains crucial: manually designed spaces require significant engineering effort, while overly flexible designs often lead to invalid or inefficient architectures. This paper introduces a novel NAS search space design that centers on symbolic constraint modeling, enabling fine-grained parametrization while ensuring architecture validity and resource efficiency. By representing parameter dependencies as symbolic expressions, our method supports automatic resolution of interdependent attributes and the specification of hard constraints, such as limits on parameter count or MAC operations, directly within the search space. This mechanism allows efficient exploration of valid architectures under strict deployment budgets. The search space itself is constructed declaratively using hierarchical, composable topology patterns, drawing from common DNN motifs and enabling intuitive and scalable definition. We demonstrate the effectiveness of our approach through evolutionary NAS under multiple resource constraints, showing that symbolic constraint enforcement improves search efficiency and robustness without sacrificing accuracy.

While automated vehicles hold the potential to significantly reduce traffic accidents, their perception systems remain vulnerable to sensor degradation caused by adverse weather and environmental occlusions. Collective perception, which enables vehicles to share information, offers a promising approach to overcoming these limitations. However, to this date collective perception in adverse weather is mostly unstudied. Therefore, we conduct the first study of LiDAR-based collective perception under diverse weather conditions and present a novel multi-task architecture for LiDAR-based collective perception under adverse weather. Adverse weather conditions can not only degrade perception capabilities, but also negatively affect bandwidth requirements and latency due to the introduced noise that is also transmitted and processed. Denoising prior to communication can effectively mitigate these issues. Therefore, we propose DenoiseCP-Net, a novel multi-task architecture for LiDAR-based collective perception under adverse weather conditions. DenoiseCP-Net integrates voxel-level noise filtering and object detection into a unified sparse convolution backbone, eliminating redundant computations associated with two-stage pipelines. This design not only reduces inference latency and computational cost but also minimizes communication overhead by removing non-informative noise. We extended the well-known OPV2V dataset by simulating rain, snow, and fog using our realistic weather simulation models. We demonstrate that DenoiseCP-Net achieves near-perfect denoising accuracy in adverse weather, reduces the bandwidth requirements by up to 23.6% while maintaining the same detection accuracy and reducing the inference latency for cooperative vehicles.

Prior theory work on Contrastive Learning via the InfoNCE loss showed that, under certain assumptions, the learned representations recover the ground-truth latent factors. We argue that these theories overlook crucial aspects of how CL is deployed in practice. Specifically, they either assume equal variance across all latents or that certain latents are kept invariant. However, in practice, positive pairs are often generated using augmentations such as strong cropping to just a few pixels. Hence, a more realistic assumption is that all latent factors change with a continuum of variability across all factors. We introduce AnInfoNCE, a generalization of InfoNCE that can provably uncover the latent factors in this anisotropic setting, broadly generalizing previous identifiability results in CL. We validate our identifiability results in controlled experiments and show that AnInfoNCE increases the recovery of previously collapsed information in CIFAR10 and ImageNet, albeit at the cost of downstream accuracy. Finally, we discuss the remaining mismatches between theoretical assumptions and practical implementations.

The energy demand of embedded systems is crucial and typically dominated by the memory subsystem. Off-the-shelf MCU platforms usually offer a wide range of memory configurations in terms of overall memory size, which may differ in the number of memory banks provided. Split memory banks have the potential to optimize energy demand, but this often remains unused in available hardware due to a lack of power management support or require significant manual effort to leverage the benefits of split-banked memory architectures. This paper proposes an approach to solve the challenge of integrating fine-grained power management support automatically, by a combined hardware/software solution for future off-the-shelf platforms. We present a method to efficiently search for an optimized code and data mapping onto the modules of split memory banks to maximize the idle times of all memory modules. To non-invasively put memory modules into sleep mode, a PC-driven power management controller (PMC) autonomously triggers transitions between power modes during embedded software execution. The evaluation of our optimization flow demonstrates that memory mappings can be explored in seconds, including the generation of the necessary PMC configuration and linker scripts. The application of PC-driven power management enables active memory modules to remain in light sleep mode for approximately 13% to 86% of the execution time, depending on the workload and memory configuration. This results in overall power savings of up to 24% in the memory banks, in terms of static and dynamic power.

RISC-V provides a flexible and scalable platform for applications ranging from embedded devices to high-performance computing clusters. Particularly, its RISC-V Vector Extension (RVV) becomes of interest for the acceleration of AI workloads. But writing software that efficiently utilizes the vector units of RISC-V CPUs without expert knowledge requires the programmer to rely on the autovectorization features of compilers or hand-crafted libraries like muRISCV-NN. Smarter approaches, like autotuning frameworks, have been missing the integration with the RISC-V RVV extension, thus heavily limiting the efficient deployment of complex AI workloads. In this paper, we present a workflow based on the TVM compiler to efficiently map AI workloads onto RISC-V vector units. Instead of relying on hand-crafted libraries, we integrated the RVV extension into TVM’s MetaSchedule framework, a probabilistic program framework for tensor operation tuning. We implemented different RISC-V SoCs on an FPGA and tuned a wide range of AI workloads on them. We found that our proposal shows a mean improvement of 46% in execution latency when compared against the autovectorization feature of GCC, and 29% against muRISCV-NN. Moreover, the binary resulting from our proposal has a smaller code memory footprint, making it more suitable for embedded devices. Finally, we also evaluated our solution on a commercially available RISC-V SoC implementing the RVV 1.0 Vector Extension and found our solution is able to find mappings that are 35% faster on average than the ones proposed by LLVM. We open-sourced our proposal for the community to expand it to target other RISC-V extensions.

The growing number of road users has significantly increased the risk of accidents in recent years. Vulnerable Road Users (VRUs) are particularly at risk, especially in urban environments where they are often occluded by parked vehicles or buildings. Autonomous Driving (AD) and Collective Perception (CP) are promising solutions to mitigate these risks. In particular, infrastructure-assisted CP, where sensor units are mounted on infrastructure elements such as traffic lights or lamp posts, can help overcome perceptual limitations by providing enhanced points of view, which significantly reduces occlusions. To encourage decision makers to adopt this technology, comprehensive studies and datasets demonstrating safety improvements for VRUs are essential. In this paper, we propose a framework for evaluating the safety improvement by infrastructure-based CP specifically targeted at VRUs including a dataset with safety-critical EuroNCAP scenarios (CarlaNCAP) with 11k frames. Using this dataset, we conduct an in-depth simulation study and demonstrate that infrastructure-assisted CP can significantly reduce accident rates in safety-critical scenarios, achieving up to 100 % accident avoidance compared to a vehicle equipped with sensors with only 33 %. Code is available at https://github.com/ekut-es/carla_ncap

Implementing Deep Neural Networks (DNNs) on resource-constrained edge devices is a challenging task that requires tailored hardware accelerator architectures and a clear understanding of their performance characteristics when executing the intended AI workload. To facilitate this, we present an automated generation approach for fast performance models to accurately estimate the latency of a DNN mapped onto systematically modeled and concisely described accelerator architectures. Using our accelerator architecture description method, we modeled representative DNN accelerators such as Gemmini, UltraTrail, Plasticine-derived, and a parameterizable systolic array. Together with DNN mappings for those modeled architectures, we perform a combined DNN/hardware dependency graph analysis, which enables us, in the best case, to evaluate only 154 loop kernel iterations to estimate the performance for 4.19 billion instructions achieving a significant speedup. We outperform regression and analytical models in terms of mean absolute percentage error (MAPE) compared with simulation results, while being several magnitudes faster than an RTL simulation.

HW-aware neural architecture search (HW-NAS) aims to yield high-accuracy neural network (NN) architectures by automatically exploring multiple architectural parameters of potential network candidates. In most HW-NAS approaches, the HW parameter search space is limited. Hence, HW awareness is tied to only a few degrees of design freedom, leading to the following sub-optimalities - First, it restricts exploration of HW parameters, which can potentially lead to better network candidates; Second, HW-NAS is still entirely a software-centric process where HW-awareness is taken care by an HW function exposed to the NAS process and is oblivious to the actual deployment. To tackle the above challenges, this paper proposes a Co-Design Neural Architecture Search (Co-NAS) approach that simultaneously explores hardware and neural architecture variations, thus allowing for full system optimization. By connecting the mutual impact of variable neural networks and HW parameters on the network's prediction accuracy and on-device efficiency in a shared optimization loop, Co-Nas finds designs of optimum performance and enables HW/SW Co-Design. This work aims to enable more diverse HW search spaces (higher degrees of design freedom) for ML accelerators (such as using a virtual prototype) and efficient exploration by integrating abstract ML accelerator and NN architecture modeling into a comprehensive Co-Nas environment. In our experiments, we explore hardware variations of a baseline accelerator architecture to demonstrate how our work can help find designs with better hardware latency and comparable network accuracy. Designs yielded by our framework provide a speedup of$1.4\times$compared to the baseline on a restricted SW search space at the same HW resources.

Several state of the art estimation and optimization techniques for CNNs and LLMs on embedded devices are summarized. For LLMs an Activation-aware Weight Quantization and on-the-fly dequantization techniques is presented. For CNNs various pruning algorithms and an integrated optimization and implementation flow is discussed. To estimate inference latency of CNNs on specific hardware platforms, three different techniques are reviewed: A mixed analytic-stochastic model, an analytic model based on step-wise linear functions, and a method that uses a detailed architecture description of the hardware.

This paper presents a demonstrator chip for an industrial audio event detection application developed as part of the Scale4Edge project. The project aims at enabling a comprehensive RISC-V based ecosystem to efficiently assemble well-tailored edge devices. The chip is manufactured in Globalfoundries' 22FDX technology and contains a RISC-V CPU with custom Instruction-Set-Architecture Extensions (ISAX) for fast AI and DSP processing, a low power neural network accelerator, and a scalable PLL to fulfill real-time processing requirements. By automated integration of these specialized hardware components, we achieve a speedup of ×2.15 while reducing the power by 27% compared to the unp[ntimized solution.

Concerns in areas such as privacy, energy consumption, climate gas emissions, and costs, push the trend of migrating neural network inference from being executed on the cloud to embedded edge devices. We present our novel approach DIA-PASON to overcome restrictions brought on by the computing and application requirements that impede their execution on resource-constrained embedded devices. Our approach addresses these challenges by distributing the inference across multiple computing instances, which could be anything ranging from a multi-CPU configuration on the same SoC to geographically distributed devices. In contrast to recent efforts which tend to apply heuristics to reduce the search space of their problem definition to solve it in a timely fashion, our novel problem definition applies the concept of continuous relaxation to the categorical selection of partitioning, layer fusion, and allocation opportunities. This approach overcomes the problem of the poor exploration of the actual search space that arises when removing potential distribution opportunities during problem simplifications. We conduct numerical simulations and ablation experiments on each one of the configuration parameters of our algorithm by distributing several widely used neural networks. Finally, we compare DIAPASON against the commonly used MoDNN baseline and a state-of-the-art approach, CoopAI, achieving a 44 % and 12 % mean speed-up respectively.

The growing concerns regarding energy consumption and privacy have prompted the development of AI solutions deployable on the edge, circumventing the substantial CO2 emissions associated with cloud servers and mitigating risks related to sharing sensitive data. But deploying Convolutional Neural Networks (CNNs) on non-off-the-shelf edge devices remains a complex and labor-intensive task. In this paper, we present an end-to-end workflow for the deployment of CNNs on Field Programmable Gate Arrays (FPGAs) using the Gemmini accelerator, which we modified for efficient implementation on FPGAs. We describe how we leverage the use of open-source software on each optimization step of the deployment process, the customizations we added to them and their impact on the final system's performance. We were able to achieve real-time performance by deploying a YOLOv7 model on a Xilinx ZCU102 FPGA with an energy efficiency of 36.5 GOP/s/W. Our FPGA-based solution demonstrates superior power efficiency compared with other embedded hardware devices and even outperforms other FPGA reference implementations. Finally, we present how this kind of solution can be integrated into a wider system, by testing our proposed platform in a traffic monitoring scenario.

Epilepsy is the most common, chronic, neurological disease worldwide and is typically accompanied by reoccurring seizures. Neuro implants can be used for effective treatment by suppressing an upcoming seizure upon detection. Due to the restricted size and limited battery lifetime of those medical devices, the employed approach also needs to be limited in size and have low energy requirements. We present an energy-efficient seizure detection approach involving a TC-ResNet and time-series analysis which is suitable for low-power edge devices. The presented approach allows for accurate seizure detection without preceding feature extraction while considering the stringent hardware requirements of neural implants. The approach is validated using the CHB-MIT Scalp EEG Database with a 32-bit floating point model and a hardware suitable 4-bit fixed point model. The presented method achieves an accuracy of 95.28%, a sensitivity of 92.34% and an AUC score of 0.9384 on this dataset with 4-bit fixed point representation. Furthermore, the power consumption of the model is measured with the low-power AI accelerator UltraTrail, which only requires 495nW on average. Due to this low-power consumption this classification approach is suitable for real-time seizure detection on low-power wearable devices such as neural implants.

Recently, there has been a great deal of research into improving AI methods and their application. The main focus is on tracking progress, enabling transparent comparisons, and fostering a more profound understanding of AI. In that process, different organizations generate and use plenty of assets that need to be tracked, traced and managed. Moreover, it is important to discover assets relevant for the task at hand. This paper presents research aiming to contribute to answering the question of what is required to exchange and manage AI models and related assets effectively without semantic gaps in an industrial context. We introduce a platform for AI model exchange, which facilitates the usage, exchange, and analysis of AI models and datasets. The platform incorporates an ontology that can foster a more profound common understanding of what is required in these tasks and help tackle the issues mentioned above. Finally, we elucidate the utility of the platform through the illustration of a use case in the context of real-time critical systems.

This work presents a simulation framework for CAN communication including attacks, with a particular focus on bus-off and WeepingCAN attacks. The simulation is validated against existing experiments, demonstrating its accuracy in replicating attack scenarios proposed by Cho et al. [11] and Bloom [2]. An intrusion detection system (IDS) is evaluated using the Hacking and Countermeasures Research Lab (HCRL) data set, and limitations in detecting WeepingCAN attacks are identified. To address these limitations, an extension to the IDS is proposed that incorporates an error frequency criterion to improve detection accuracy. The extended IDS is evaluated in different environments, demonstrating its effectiveness in reliably distinguishing between normal communications and WeepingCAN attacks. Overall, this work contributes to the understanding and detection of sophisticated attacks on CAN and and offers support to develop and evaluate further detection mechanisms.

To ensure safe operation of autonomous vehicles in complex urban environments, complete perception of the environment is necessary. However, due to environmental conditions, sensor limitations, and occlusions, this is not always possible from a single point of view. To address this issue, collective perception is an effective method. Realistic and large-scale datasets are essential for training and evaluating collective perception methods. This paper provides the first comprehensive technical review of collective perception datasets in the context of autonomous driving. The survey analyzes existing V2V and V2X datasets, categorizing them based on different criteria such as sensor modalities, environmental conditions, and scenario variety. The focus is on their applicability for the development of connected automated vehicles. This study aims to identify the key criteria of all datasets and to present their strengths, weaknesses, and anomalies. Finally, this survey concludes by making recommendations regarding which dataset is most suitable for collective 3D object detection, tracking, and semantic segmentation.

Comprehensive perception of the vehicle’s environment and correct interpretation of the environment are crucial for the safe operation of autonomous vehicles. The perception of surrounding objects is the main component for further tasks such as trajectory planning. However, safe trajectory planning requires not only object detection, but also the detection of drivable areas and lane corridors. While first approaches consider an advanced safety evaluation of object detection, the evaluation of lane detection still lacks sufficient safety metrics. For assessing safety, additional factors such as the semantics of the scene with road type and road width, the detection range as well as the potential causes of missing detections, incorporated by vehicle speed, should be considered for the evaluation of lane detection. Therefore, we propose the Lane Safety Metric (LSM), which takes these factors into account in order to evaluate the safety of lane detection systems by determining an easily interpretable safety score. We evaluate our offline safety metric on various virtual scenarios using different lane detection approaches and compare it with state-of-the-art performance metrics.

In this article, we rethink the dataflow processing paradigm to a higher level of abstraction to automate the generation of multi-instance compute and memory platforms with interfaces to I/O devices (sensors and actuators). Since the different compute instances (NPUs, CPUs, DSPs, etc.) and I/O devices do not necessarily have compatible interfaces on a dataflow level, an automated translation is required. However, in multidimensional dataflow scenarios, it becomes inherently difficult to reason about buffer sizes and iteration order without knowing the shape of the data access pattern (DAP) that the dataflow follows. To capture this shape and the platform composition, we define a domain-specific representation (DSR) and devise a toolchain to generate a synthesizable platform, including appropriate streaming buffers for platform-specific tensorization of the data between incompatible interfaces. This allows platforms, such as sensor edge AI devices, to be easily specified by simply focusing on the shape of the data provided by the sensors and transmitted among compute units, giving the ability to evaluate and generate different dataflow design alternatives with significantly reduced design time.

Co-optimization of hardware and software in modern deep neural network (DNN) systems can be performed using design space exploration (DSE) tools. Leveraging estimation models to predict design decisions' impact on the system's performance allows a fast evaluation of up to billions of architectural choices. In this work, we propose SimPyler, an end-to-end framework for latency estimations of DNN workloads on machine learning (ML) accelerators. SimPyler represents DNN kernels as graphs executed on abstract accelerator models to simulate the system's latency. By generating the entire simulation infrastructure automated from the DNN operator description, the framework can flexibly adjust to changes at the hardware or algorithmic level, enabling the usage in DSE applications. A key enabler in this automation process is a machine-learning compiler. The framework is implemented in Python, using only open-source software. We demonstrate and validate the proposed methodology by modeling different single-core and multi-core hardware architectures and DNNs, comparable to state-of-the-art. Our experiments show we can estimate the end-to-end latency with an average error of 4.12%

Comprehensive environment perception is essential for autonomous vehicles to operate safely. It is crucial to detect both dynamic road users and static objects like traffic signs or lanes as these are required for safe motion planning. However, in many circumstances a complete perception of other objects or lanes is not achievable due to limited sensor ranges, occlusions, and curves. In scenarios where an accurate localization is not possible or for roads where no HD maps are available, an autonomous vehicle must rely solely on its perceived road information. Thus, extending local sensing capabilities through collective perception using vehicle-to-vehicle communication is a promising strategy that has not yet been explored for lane detection. Therefore, we propose a real-time capable approach for collective perception of lanes using a spline-based estimation of undetected road sections. We evaluate our proposed fusion algorithm in various situations and road types. We were able to achieve real-time capability and extend the perception range by up to 200%.

The vulnerability of vehicles due to the lack of security features of the Controller Area Network (CAN) is now well known. CAN is one of the de facto standards for internal vehicle communication, so securing CAN against attacks is an ongoing challenge. For this purpose, Intrusion Detection Systems (IDS) are a widely known approach for attack detection. IDS have to be trained and evaluated, therefore data is needed. The few publicly available data sets cover only a small variance of possible attacks. Since conducting real attacks can be a costly business, the presented method generates simulated attack data that can be used to train and evaluate IDS. To show the vulnerabilities of an IDS, the approach adapted the attacks so that they are not detected by the IDS. The approach is executed on an IDS that detected 99.99% of the original attacks in the publicly available data sets. After adaptation by the proposed method, we found several attacks that were not detected.

LiDAR-based perception systems have become widely adopted in autonomous vehicles. However, their performance can be severely degraded in adverse weather conditions, such as rain, snow or fog. To address this challenge, we propose a method for improving the robustness of LiDAR-based perception in adverse weather, using data augmentation techniques on point clouds. We use novel as well as established data augmentation techniques, such as realistic weather simulations, to provide a wide variety of training data for LiDAR-based object detectors. The performance of the state-of-the-art detector Voxel R-CNN using the proposed augmentation techniques is evaluated on a data set of real-world point clouds collected in adverse weather conditions. The achieved improvements in average precision (AP) are 4.00 p.p. in fog, 3.35 p.p. in snow, and 4.87 p.p. in rain at moderate difficulty. Our results suggest that data augmentations on point clouds are an effective way to improve the robustness of LiDAR-based object detection in adverse weather.

We present an automatic methodology to accurately predict the performance of Deep Neural Network (DNN) accelerators using abstract descriptions of accelerator architectures and DNNs with a high degree of flexibility. By mapping partially unrolled neural network layers onto accelerator architectures, we automatically construct an analytical performance model, exploiting the dataflow-driven nature of DNNs that allows us to evaluate only a few loop iterations to determine the performance of a whole DNN layer.

This paper introduces the project Scale4Edge. The project is focused on enabling an effective RISC-V ecosystem for optimization of edge applications. We describe the basic components of this ecosystem and introduce the envisioned demonstrators, which will be used in their evaluation.

The increasing spread of artificial neural networks does not stop at ultralow-power edge devices. However, these very often have high computational demand and require specialized hardware accelerators to ensure the design meets power and performance constraints. The manual optimization of neural networks along with the corresponding hardware accelerators can be very challenging. This paper presents HANNAH (Hardware Accelerator and Neural Network seArcH), a framework for automated and combined hardware/software co-design of deep neural networks and hardware accelerators for resource and power-constrained edge devices. The optimization approach uses an evolution-based search algorithm, a neural network template technique and analytical KPI models for the configurable UltraTrail hardware accelerator template in order to find an optimized neural network and accelerator configuration. We demonstrate that HANNAH can find suitable neural networks with minimized power consumption and high accuracy for different audio classification tasks such as single-class wake word detection, multi-class keyword detection and voice activity detection, which are superior to the related work.

Scenario-based approaches for the validation of highly automated driving functions are based on the search for safety-critical characteristics of driving scenarios using software-in-the-loop simulations. This search requires information about the shape and probability of scenarios in real-world traffic. The scope of this work is to develop a method that identifies redefined logical driving scenarios in field data, so that this information can be derived subsequently. More precisely, a suitable approach is developed, implemented and validated using a traffic scenario as an example. The presented methodology is based on qualitative modelling of scenarios, which can be detected in abstracted field data. The abstraction is achieved by using universal elements of an ontology represented by a domain model. Already published approaches for such an abstraction are discussed and concretised with regard to the given application. By examining a first set of test data, it is shown that the developed method is a suitable approach for the identification of further driving scenarios.

The threat to modern cars is increasing due to their growing connectivity to the outside world. Attacks targeting the Controller Area Network (CAN), the internal communication network of vehicles, can have a fatal outcome. To detect attacks on the CAN, communication data is needed. The generation of such data is very time-consuming with real vehicles, if both the possible environmental conditions and the different driving maneuvers are taken into account. The presented approach therefore simulates CAN communication with and without attacks, taking into account the environmental conditions and the operations of the vehicle.

For robust object detection on LiDAR data, neural networks have to be trained on diverse datasets that contain many different environmental influences like rain, snow, or fog. To this date, few datasets, with those features, are available while there exist many datasets recorded under perfect weather conditions. Repurposing those datasets by simulating adverse environmental conditions on top of them and training networks with the resulting enhanced datasets, is intended to lead to more robust neural networks. In the following we propose models to realistically simulate the effects of rain, snow, and fog on LiDAR datasets based on physical and empirical fundamentals. Then we parameterize our simulation to best fit real LiDAR data that was captured in those environments, in order to achieve a highly accurate simulation. Finally, the impact of adverse weather on neural network detection performance is demonstrated.

In recent years artificial neural networks (NNs) have been at the center of research on data processing. However, their high computational demand often prohibits deployment on resource-constrained Industrial IoT Systems. Custom hardware accelerators can enable real-time NN processing on small-scale edge devices but are generally hard to develop and integrate. In this paper we present a hardware generation approach to rapidly create, test, and deploy entire SoC platforms with application-specific NN hardware accelerators. The feasibility of the approach is demonstrated by the generation of a condition monitoring system for high-speed valves.

The successful application of static program analysis strongly depends on flow facts of a program such as loop bounds, control-flow constraints, and operating modes. This problem heavily affects the design of real-time systems, since static program analyses are a prerequisite to determine the timing behavior of a program. For example, this becomes obvious in worst-case execution time (WCET) analysis, which is often infeasible without user-annotated flow facts. Moreover, many timing simulation approaches use statically derived timings of partial program paths to reduce simulation overhead. Annotating flow facts on binary or source level is either error-prone and tedious, or requires specialized compilers that can transform source-level annotations along with the program during optimization. To overcome these obstacles, so-called scenarios can be used. Scenarios are a design-time methodology that describe a set of possible system parameters, such as image resolutions, operating modes, or application-dependent flow facts. The information described by a scenario is unknown in general but known and constant for a specific system. In this article, 1 we present a methodology for scenario-aware program specialization to improve timing predictability. Moreover, we provide an implementation of this methodology for embedded software written in C/C++. We show the effectiveness of our approach by evaluating its impact on WCET analysis using almost all of TACLeBench–achieving an average reduction of WCET of 31%. In addition, we provide a thorough qualitative and evaluation-based comparison to closely related work, as well as two case studies.

Fast and accurate predictions of a program's execution time are essential during the design space exploration of embedded systems. In this paper, we present a novel approach for efficient context-sensitive timing simulations based on the LLVM IR code representation. Our approach allows evaluating simultaneously multiple hardware platform configurations with only one simulation run. State-of-the-art solutions are improved by speeding up the simulation throughput relying on the fast LLVM IR JIT execution engine. Results show on average over 94% prediction accuracy and a speedup of 200 times compared to interpretive simulations. The simulation performance reaches up to 300 MIPS when one HW configuration is assessed and it grows up to 1 GIPS evaluating four configurations in parallel. Additionally, we show that our approach can be utilized for producing early timing estimations that support the designers in mapping a system to heterogeneous hardware platforms.

The remaining useful life (RUL) estimation of a component is a core aspect in the implementation of a predictive maintenance policy for mechanical systems. Several novel deep learning approaches have already been developed to forecast the failure of a particular system or element. Most of them focus only on the improvement of the accuracy and thus, very complex deep architectures are generated to solve the RUL prediction task. However, such complex models can hardly be implemented in an embedded system. Thus, they could not be suitable for applications such as the condition monitoring of vehicles or mobile robots. On the other hand, we propose a new architecture named Multipath Temporal Convolutional Network (MTCN), which is based on residual networks. This novel architecture enables an accurate prediction of the time to failure (TTF) of a system and simultaneously reduces the computation complexity. Moreover, the hyperparameters of the network are optimized with a genetic algorithm (GA). We validate the efficiency of our approach by using the C-MAPSS database and perform a direct comparison with the state of the art approaches for failure prognosis. The experimental study validates the high performance of MTCNs to solve the RUL prediction task with a minimal computational complexity in comparison to other published approaches. This will enable the deployment of MTCN for on-board monitoring applications of mobile systems in future research.

Modeling and validation of complex and highly connected systems involved in safety-critical tasks are great challenges today with little support in automation. A graph structure models the system and the faults component-by-component in the proposed approach and specifies valid systems. Automated generation and execution of test cases for every valid combination of components is done as well as monitoring and assessment of the system behavior. The integrated fault description provides faults from single bit-flip to comprehensive scenarios. The simulation is supervised and executed by the graph, which adapts the faults automatically during simulation with respect to the simulation state.

The paper presents an efficient approach to the semantic enrichment of measured sensor data in Wireless Sensor Networks (WSNs), by bridging techniques from Model-driven Software Development (MDSD) and Semantic Web Technology (SWT). Our approach reinforces data interoperability, fostering data sharing and reuse, by utilizing SWT. Model-based and type-agnostic configuration reduces the overall effort for WSN setup and maintenance, which are traditionally complex and time-consuming tasks. The presented approach addresses the problem of large-scale WSN management through the application of SWT in WSN configuration and management without requiring expert knowledge. Additionally, we present a generic architecture and an implementation which is also supplemented by hands-on descriptions of an illustrative use case. Our experimental results demonstrate that our model-based approach provides non-intrusive semantic enrichment with sub-millisecond computational overhead, as well as partially automated configuration of WSNs.

We present a methodology for fast cycle-accurate gate-level power density analysis especially suited for hard macros. It leverages a post-PAR (place and route) design. The proposed model generation flow consists of three automated steps: partitioning the design into estimation regions, generating power models using gate-level simulation, estimating power dissipation and power density using a higher-level simulation engine (RTL or above). Our models are based on signal transition classification, which factors in the changes in circuit state caused by signal transitions, and corresponding lookup-tables. Our implementation shows a speedup of 320x for an open source processor (1800x for a multiplier) compared to a state-of-the-art commercial tool.

Today’s state-of-the-art machine vision models are vulnerable to image corruptions like blurring or compression artefacts, limiting their performance in many real-world applications. We here argue that popular benchmarks to measure model robustness against common corruptions (like ImageNet-C) underestimate model robustness in many (but not all) application scenarios. The key insight is that in many scenarios, multiple unlabeled examples of the corruptions are available and can be used for unsupervised online adaptation. Replacing the activation statistics estimated by batch normalization on the training set with the statistics of the corrupted images consistently improves the robustness across 25 different popular computer vision models. Using the corrected statistics, ResNet-50 reaches 62.2% mCE on ImageNet-C compared to 76.7% without adaptation. With the more robust DeepAugment+AugMix model, we improve the state of the art achieved by a ResNet50 model up to date from 53.6% mCE to 45.4% mCE. Even adapting to a single sample improves robustness for the ResNet-50 and AugMix models, and 32 samples are sufficient to improve the current state of the art for a ResNet-50 architecture. We argue that results with adapted statistics should be included whenever reporting scores in corruption benchmarks and other out-of-distribution generalization settings.

Recent advances in machine learning show the superior behavior of temporal convolutional networks (TCNs) and especially their combination with residual networks (TC-ResNet) for intelligent sensor signal processing in comparison to classical CNNs and LSTMs. In this article, we propose UltraTrail, a configurable, ultralow-power TC-ResNet AI accelerator for sensor signal processing and its application to efficient keyword spotting (KWS). Following a strict hardware/model co-design approach, we have derived an optimized low-power hardware architecture for generalized TC-ResNet topologies consisting of a configurable array of processing elements and a distributed memory with dynamic content reallocation. We additionally extend the network with conditional computing to reduce the number of operations during inference and to provide the possibility for power-gating. The final accelerator implementation in Globalfoundries' 22FDX technology achieves a power consumption of 8.2 μW for the task of always-on KWS meeting the real-time requirement of 100 ms per inference with an accuracy of 93% on the Google Speech Command Dataset.

In the early 1980s, Wolfgang Rosenstiel was a student of Computer Science at the University of Karlsruhe (KIT). During the next 40 years, we worked together at times, we met at numerous conferences and workshops, we visited each other regularly, and above all we became good friends. He was a person with an extraordinary capacity for work with a contagiously positive and optimistic outlook, an excellent researcher and teacher, involved in many aspects of our profession.

Nowadays, product lines are common practice in the embedded systems domain as they allow for substantial reductions in development costs and the time-to-market by a consequent application of design paradigms such as variability and structured reuse management. In that context, accurate and fast timing predictions are essential for an early evaluation of all relevant variants of a product line concerning target platform properties. Context-sensitive simulations provide attractive benefits for timing analysis. Nevertheless, these simulations depend strongly on a single configuration pair of compiler and hardware platform. To cope with this limitation, we present SIMULTime, a new technique for context-sensitive timing simulation based on the software intermediate representation. The assured simulation throughput significantly increases by simulating simultaneously different hardware hardware platforms and compiler configurations. Multiple accurate timing predictions are produced by running the simulator only once. Our novel approach was applied on several applications showing that SIMULTime increases the average simulation throughput by 90% when at least four configurations are analyzed in parallel.

We present a methodology for automatic synthesis of power management controllers for System-on-Chip designs by using an extended version of the Unified Power Format (UPF). Our methodology takes an SoC design and a UPF-based power design, and automatically generates a power management controller in Verilog/VHDL that implements the power state machine specified in UPF. It performs a priority-based scheduling for all power state machine actions, connects each power management signal to the corresponding logic wire in the UPF design and integrates the controller into the System-on-Chip using a configurable bus interface. We implemented the proposed approach as a plugin for Synopsys Design Compiler to close the gap in today's power management flows and evaluated it by a RISC-V System-on-Chip.

The use of pedelecs as a mobility solution has increased considerably in recent years. One of their main components, the drive unit, consists of several mechanical elements such as bearings and gears, which deteriorate over time and, thus, increasing the probability of a major failure. This work introduces a data-based approach for monitoring the drive unit's condition and forecasting failures, in order to ensure the reliability of the system. A trustworthy prediction of anomalies requires a vast dataset to train and test the selected algorithms. To this end, we make use of a database consisting of data collected for the past couple of years during endurance tests of almost one hundred drive units. The collected database allow us to test machine learning approaches under more realistic prognosis applications in comparison to existing published works, which brings diverse challenges such as unlabeled and unbalaced data. The focus of the present approach is the data preprocessing through different stages, such as data labeling and undersampling, to reduce the negative impact of the problematics that involve this database. Afterwards, a Gaussian process for regression is trained with these preprocessed data to predict the remaining useful life of the drive unit. The experimental study shows that by performing these preprocessing stages, an accurate estimation of the time to failure of the drive unit can be achieved.

Small embedded devices are highly specialized plat forms that integrate several peripherals alongside the CPU core. Embedded devices extensively rely on Firmware (FW) to control and access the peripherals as well as other important functionality. This poses challenges to FW development since the FW must be adapted to each specific device configuration. Besides ensuring functional correctness to avoid errors and security vulnerabilities, an important design factor today is the control and adaptivity of a system with respect to non-functional properties, like for example application-specific timing budgets. Furthermore, optimizations of the FW and HW/SW interface play a very important role due to the tight resource constraints of small embedded devices. To satisfy these requirements new FW design methods are needed targeting FW generation, FW verification and FW optimization.This paper presents such new methods to enable an early, efficient and systematic FW design taking the underlying HW architecture into account. We use the RISC-V Instruction Set Architecture (ISA) as a case study to demonstrate our methods.

Autonomous vehicles need a complete and robust perception of their environment to correctly understand the surrounding traffic scene and come to the right decisions. Making use of vehicle-to-vehicle (V2V) communication can improve the perception capabilities of autonomous vehicles by extending the range of their own local sensors. For the development of robust cooperative perception systems it is necessary to include varying environmental conditions to the scenarios used for validation. In this paper we present a new approach to investigate a cooperative perception pipeline within simulation under varying rain conditions. We demonstrate our approach on the example of a complete vision-based cooperative perception pipeline. Scenarios with a varying number of cooperative vehicles under different synthetically generated rain variations are used to show the influence of rain on local and cooperative perception.

A large variety of data is serialized and exchanged using XML. Model-driven activities can benefit from XML data, as shown by various approaches to IP-XACT and UML integration. However, these approaches are inherently time consuming, error-prone, and inflexible due to the manual effort involved. We propose an automated framework for integrating arbitrary XML data into UML models using an automatically generated UML profile corresponding to the structure of the XML data. User-defined XML-to-UML mappings further enhance this integration. Our approach mitigates the aforementioned issues while providing the same benefits.

In this paper, we present a methodology for the automatic detection of non-functional circuit activity in SoC designs. Our methodology formally analyses an RTL design, generates an internal graph representation and traverses the graph using given simulation traces. We evaluate an open source processor with a given set of benchmark applications using our approach. With a commercial RTL simulator, we observe an average register toggle activity of 6.7%-11.5%, but our experiments show that 86.1-92.7% of these toggles are non-functional, i.e. not necessary for producing the exact same circuit output. We further evaluate the efficiency of the clock gating architecture of a commercial ASIP. For the Dhrystone benchmark we show that, even though only 34.7% of the registers are clocked on average, still 64.3% of the non-clock-gated registers in this ASIP are not needed on average to produce exactly the same circuit output.

Source-level timing simulation (STLS) is an important technique for early examination of timing behavior, as it is very fast and accurate. A factor occasionally more important than precision is simulation speed, especially in design space exploration or very early phases of development. Additionally, practices like rapid prototyping also benefit from high-performance timing simulation. Therefore, we propose to further reduce simulation run-time by utilizing a method called loop acceleration. Accelerating a loop in the context of SLTS means deriving the timing of a loop prior to simulation to increase simulation speed of that loop. We integrated this technique in our SLTS framework and conducted an comprehensive evaluation using the Malardalen benchmark suite. We were able to reduce simulation time by up to 43% of the original time, while the introduced accuracy loss did not exceed 8 percentage points.

Security by Design becomes a significant aspect for establishing the Internet-of-Things (IoT) paradigm. In this paper, we present an approach to utilize virtual prototypes (VP) at system level to enable security evaluation along the design process. The proposed VP-based penetration testing framework provides an approach for attack surface and attack behavior modeling. By utilizing a modular, reconfigurable system simulation, an attack scenario can be assessed with different system alternatives. As the VP simulates both hardware (HW) and software (SW) of a single IoT-device as well as the interconnections of different devices a comprehensive system analysis can be executed. Our framework is based on a model-driven approach, which underlines the achieved degree of automation and its potential for industrial application. A comprehensive system analysis tool is the enabler to apply penetration testing, for identifying weak points in the system design and implementation, from early stages in the design flow. The overall approach is demonstrated by an automotive use case derived from real-world security flaws.

The stress of verifying and validating nowadays complex systems is continuously boosting. To address this imperative issue, we present an optimised assertion checking approach that dynamically implements an instruction-based checker to validate system properties during run-time. In contrast to state-of-the-art hardware checker, the presented method compiles an assertion to a microprogram, which can be changed very flexibly by software for the in-silicon validation. A stand-alone hardware block, named assertion checking unit (ACU), is designed for executing the compiled microprogram in real-time. We have successfully evaluated this approach to detect run-time error of a prototyped cryptographic system by means of a run-time fault injection technology. Additionally, we have achieved measurable benefits of the new approach compared to the previous work.

This paper presents an ontology-supported approach to the management of design parameters in engineering. This approach aims specifically at enabling Change Impact Analysis through Requirements Traceability and acquainted expert knowledge of design parameters. The approach is suitable for both software and hardware designs. The activities and features are mainly obtained by (1) the application of an ontology-based universal system modeling procedure proposal for model integration, (2) the utilization of a knowledge base for capturing expert knowledge and (3) a semantic Mission Profile Aware Design platform. OWL is used to represent information and the underlying data model can improve knowledge transfer among heterogeneous systems which are common in complex engineering projects. At the same time, effort to perform reasoning on such models can be reduced. A demonstration and hands-on description of two illustrative use cases complements the paper.

The latest developments in networking and the rapidly increasing demand for IoT devices lead to higher demands on time-to-market and production costs. In addition, the complexity of the development processes for smart sensor ASICs is constantly increasing and new methods for automation and code generation are particularly needed in development. This paper describes a new methodology that formalizes functional specification based on SysML and enables automation of Virtual Prototype (VP) development. The virtual prototype is an established approach for early embedded software development. The presented methodology translates natural language written specifications into a modeled and formalized functional specification and enables the generation of behavior descriptions in SystemC that are used for the creation of VP. Furthermore, it enables the connection of the IP-XACT-centric generation of the register interface description, as well as the description of the signal processing parts by MATLAB®Simulink®, with the SysML-based generated functional description.

Recent developments in the field of autonomous cars indicate the appearance of those vehicles on the streets of every city in the near future. This urban driving requires zero error tolerance. In order to guarantee safety requirements self-driving cars and the used software have to pass exhaustive tests under as many different conditions as possible. The more versatile the considered influences and the more thorough the tests made under those influences, the safer the car will drive under real conditions. Unfortunately, it is very time and resource intensive to record the same test set of images over and over again, every time producing, or hoping for, specific conditions; especially when using real test vehicles. This is where environment simulation comes into play. This research investigates the simulation of environmental influences which may affect the sensors used in autonomous vehicles, in particular how raindrops resting on a windshield affect cameras as they may occlude large parts of the field of view. We propose a novel method to render these raindrops using Continuous Nearest Neighbor search leveraging the benefits of R-trees. The 3D scene in front of the camera, which is generated from stereo images, reflects physically correct in these drops. This leads to near photo-realistic simulated results. The derived images may be used to extend the training data sets used for machine learning without being forced to capture new real pictures.

We present a novel technique for efficient source level timing simulation of embedded software execution on a target platform. In contrast to existing approaches, the proposed technique can accurately approximate time without requiring a dynamic cache model. Thereby the dramatic reduction in simulation performance inherent to dynamic cache modeling is avoided. Consequently, our approach enables an exploitation of the performance potential of source level simulation for complex microarchitectures that include caches. Our approach is based on recent advances in context-sensitive binary level timing simulation. However, a direct application of the binary level approach to source level simulation reduces simulation performance similarly to dynamic cache modeling. To overcome this performance limitation, we contribute a novel pushdown automaton based simulation technique. The proposed context-sensitive timing automata enable an efficient evaluation of complex simulation logic with little overhead. Experimental results show that the proposed technique provides a speed up of an order of magnitude compared to existing context selection techniques and simple source level cache models. Simulation performance is similar to a state of the art accelerated cache simulation. The accelerated simulation is only applicable in specific circumstances, whereas the proposed approach does not suffer this limitation.

Model-based Systems Engineering requires an intuitive semantically strong data model to enable precise data specification and provide the foundation for fruitful data analyses during data evolution. This paper presents an approach to use the Web Ontology Language (OWL) for specifying a Conceptual Data Model (CDM) being transformed into a format understandable by the Eclipse Modeling Framework (EMF) to profit from powerful data handling and knowledge management functions during runtime. Coalescing OWL with EMF brings up the strength of both approaches leading to considerably better data models with less failure potential and reveal notably more analysis potential by using a common data model specification. This approach also enables the direct application of reasoning functionality for automatic inference of several pieces of knowledge and automatic checks as illustrated by examples from aerospace industry.

We present a fast and accurate timing simulation of binary code execution on complex embedded processors. Underlying block timings are extracted from a preceding hardware execution and differentiated by execution context. Thereby, complex factors, such as caches, can be reflected accurately without explicit modeling. Based on timings observed in one hardware execution, timing of numerous other executions for different inputs can be simulated at an average error below 5% for complex applications on an ARM Cortex-A9 processor.

We propose a methodology for the generation of sleep modes traces. Sleep mode traces identify idle times of components in a design and are used in state-of-the-art power optimization approaches. While designers are currently forced to generate them manually, our graph-based method enables a full automation of this process. We implemented our methodology in a framework, that we call SMoSi. Experiments show that SMoSi generates sleep mode traces in reasonable time for a given design.

In FDSOI, sophisticated body biasing schemes can greatly reduce leakage or improve performance as well as efficiency. This paper proposes algorithms to determine body bias domain candidates which then merge those to reach a desired number of domains. Domain candidates are determined using an activation based approach, analyzing mapped verilog netlists to identify which parts of the design are used under specified conditions. Body bias domain partitionings are then determined based on activation and the timing of the partitioned parts. The algorithms include a body bias assignment algorithm to reach given timing goals with multiple domains and cross-domain resource sharing. The approach is compatible with any synthesis optimization and is resource sharing aware. Using an implementation of the proposed algorithms, overall leakage can be significantly reduced in all scenarios while obtaining the same benefits of body biasing. The method is evaluated in STMicro's 28nm FDSOI and Renesas's 65nm SOTB.

The heating system, the second largest energy consumer after the power train in electric vehicles (EV), has a significant impact on the overall energy management. We propose an optimized control algorithm for minimizing the energy consumption of the heating system for the passenger cabin. The presented adaptive control strategy combining a learning algorithm and dynamic programming optimizes the amount of energy consumption under consideration of the thermal comfort of EV passengers. Experiments shows that a reduction of energy consumption up to 12 % is achieved without sacrificing the preferred comfort.

Recently, Assertion-Based Verification (ABV) has been significantly improved and used not only in academia but also in industry. In this paper, we present a new assertion checking approach that dynamically interprets a software-defined assertion checker during run-time. In contrast to the state-of-the-art hardware checker, the presented method compiles its checker to instructions, which can be changed flexibly by software in the in-silicon phase. A stand-alone hardware block, called assertion processing unit (APU), is used for implementing the compiled instructions. This unit handles the storage of the checker code, the execution of the checking, and the feedback of checked results in the system run-time environment. We have successfully evaluated this approach on an FPGA-based prototyping board, showing measurable benefits of this approach.

In this paper we perform an impact analysis of the AUTOSAR energy saving mechanisms partial networking and pretended networking for automotive networks. We developed novel energy management strategies by exploiting these mechanisms. The strategies are integrated in a multi-level power management framework, which consists of three levels. Based on these strategies, we performed experiments on two production-class Electric Vehicles (EVs) measuring the energy consumption of the Electronic Control Units (ECUs). Results show up to 75.4% energy saving impact on the ECUs energy consumption on our test drives.

This paper presents a novel methodology for deriving Conceptual Data Models in the scope of Model-based Systems Engineering. Based on an assessment of currently employed methodologies, substantial limitations of the state of the art are identified. Consequently, a new methodology, overcoming present shortcomings, is elaborated, containing detailed and prescriptive guidelines for deriving conceptual data models used for representing engineering data in a multi-disciplinary design process. For highlighting the applicability and benefits of the approach, the derivation of a semantically strong conceptual data model in the context of Model-based Space Systems Engineering is presented as a case study.

This paper presents the design and usage of a language for Conceptual Data Modeling in Model-based Systems Engineering. Based on an existing analysis of presently employed data modeling languages, a new conceptual data modeling language is defined that brings together characteristic features from software engineering languages, features from languages classically employed for knowledge engineering, as well as entirely newly developed functional aspects. This language has been applied to model a spacecraft as an example, demonstrating its utility for developing complex, multidisciplinary systems in the scope of Model-based Space Systems Engineering.

This paper presents an approach on extending virtual prototyping, commonly used for system verification and design space exploration, for safety analysis. Virtual prototyping will enhance safety analysis, overcoming the challenges resulting from the ever-increasing number of safety-related, complex, interconnected electronic systems. The presented integral fault injection framework enables safety analysis in combination with established system verification methods. It consists of a fault behavior specification methodology and the corresponding, reusable injection tool, with focus on seamless applicability in between functional models in early concept phases and low-level structural models in late design phases. Our approach works with third party compilers and simulators while providing a minimal intrusive approach using existing models. Selected use cases at gate, register-transfer and functional level demonstrate the usage of the approach.

Providing secure access to confidential information is extremely difficult, notably when regarding weak endpoints and users. With the increasing number of corporate espionage cases and data leaks, a usable approach enhancing the security of data on endpoints is needed. In this paper we present our implementation for providing a new level of security for confidential documents that are viewed on a display. We call this End-to-Display Encryption (E2DE). E2DE encrypts images in the pixel-domain before transmitting them to the user. These images can then be displayed by arbitrary image viewers and are sent to the display. On the way to the display, the data stream is analyzed and the encrypted pixels are decrypted depending on a private key stored on a chip card inserted in the receiver, creating a viewable representation of the confidential data on the display, without decrypting the information on the computer itself. We implemented a prototype on a Digilent Atlys FPGA Board supporting resolutions up to Full HD.

In this paper we propose an approach on energy management for optimizing the energy consumption of both electrical and conventional vehicle's board electronic. The pursued idea exploits degrees of freedom resulting from vehicle functions which are not permanently used during operation. The elaborated framework achieves this by a state-based power optimization approach using partial networking. It selectively shuts down Electronic Control Units (ECUs) based on requirement and criticality. Experimental results show up to 29.6% saving of the ECUs energy consumption on several driving cycles, which were created from real measured data provided by an automotive OEM.

We propose a novel torque vectoring concept for battery electric vehicles propelled by wheel-individual electric machines. Besides vehicle dynamic aspects, mainly addressed in other works, we especially focus on energy efficiency improvements. Our approach is based on a comprehensive four-wheel model taking the tires' nonlinear characteristics into account. A yaw torque optimized for vehicle dynamics and energy efficiency is calculated by a controller and allocated to the wheel hubs by a torque distribution block considering the efficiency characteristics of the electric machines. The resulting torque vectoring control system leads to an energy consumption reduction of around 10% for many driving situations, containing both high and low lateral acceleration scenarios.

The engineering of complex systems is more and more supported through computer-based models that rely on a comprehensive specification of their underlying data. This paper reflects on extensive industrial experience with a sophisticated application of conceptual data modeling, addressing requirements as they arise in the context of space systems engineering. For this purpose identified needs for conceptual data modeling in the scope of Model-Based Systems Engineering are formulated. Established and evolving approaches and technologies for building conceptual data models are characterized, analyzed, and discussed regarding their suitability for modeling engineering data. Based on this analysis of the state of the art, recommendations for the future evolution of conceptual data modeling are formulated.

To overcome the verification gap arising from significantly increased external IP integration and reuse during electronic platform design and composition, we present a model-based approach to specify platform variants. The variants specification is processed automatically by formalizing and solving the integrated constraint sets to derive valid platforms. These constraint sets enable a precise specification of the required platform variants for verification, exploration and test. Experimental results demonstrate the applicability, versatility and scalability of our novel model-based approach.

We present an approach to accurately simulate the temporal behavior of binary embedded software based on timing data generated using static analysis. As the timing of an instruction sequence is significantly influenced by the microarchitecture state prior to its execution, which highly depends on the preceding control flow, a sequence must be separately considered for different control flow paths instead of estimating the influence of basic blocks or single instructions in isolation. We handle the thereby arising issue of an excessive or even infinite number of different paths by considering different execution contexts instead of control flow paths. Related approaches using context-sensitive cycle counts during simulation are limited to simulating the control flow that could be considered during analysis. We eliminate this limitation by selecting contexts dynamically, picking a suitable one when no predetermined choice is available, thereby enabling a context-sensitive simulation of unmodified binary code of concurrent programs, including asynchronous events such as interrupts. In contrast to other approximate binary simulation techniques, estimates are conservative, yet tight, making our approach reliable when evaluating performance goals. For a multi-threaded application the simulation deviates only by 0.24% from hardware measurements while the average overhead is only 50% compared to a purely functional simulation.

Intelligent automotive electronics significantly improved driving safety in the last decades. With the increasing complexity of automotive systems, dependability of the electronic components themselves and of their interaction must be assured to avoid any risk to driving safety due to unexpected failures caused by internal or external faults.

In this paper we propose to exploit so called Mission Profiles to address increasing requirements on safety and power efficiency for automotive power ICs. These Mission Profiles constrain the required device performance space to valid application scenarios. Mission Profile data can be represented in arbitrary forms like temperature histograms or cumulated drive cycle data. Hence, the derivation of realistic verification scenarios on device level requires the generation of environmental properties as e.g. temperatures, board net conditions or currents. For the assessment of real application robustness we present a methodology to extract finite state machines out of measured vehicle data and integrate them in Mission Profiles. Subsequently Markov processes are derived from these finite state machines in order to automatically generate Mission Profile compliant test scenarios for the design and verification process. As a motivating example we show industry fault cases in which missing application fitness to power transient variations finally results in device failure. Verification results based on lab data are outlined and show the benefits of a fully mission profile driven IC verification flow.

This paper presents a real-time capable battery aging estimation to enhance state-of-the-art eco-driving concept with battery maintenance strategy for potentially advancing electric vehicles (EV) sustainability. This methodology focuses not only on estimating battery aging according to the input parameters during driving and resting period but also optimizing withdrawn battery power. This is derived from applied control strategy for state of charge (SoC) and state of health (SoH) modeling. A systematic lithium-based battery model with temperature significance is established as the base of this methodology which is validated under actual operating conditions. The result indicates that eco-driving strategy is advanced by SoH in parallel with SoC estimation, also the optimization of withdrawn battery power might be further adapted to establish advanced driving range prediction. Particularly, the real-time implementation of this methodology might increase the awareness of EV drivers for preventing any accelerated battery aging.

We propose a novel operation strategy for electric vehicles with axle-individual electric machines to improve their energy efficiency in typical driving situations. The developed algorithm is allocating a total torque requested by a velocity controlling system or the driver to the electric machines such that the energy loss is reduced compared to an equal distribution. By taking near-future forecasts into account, the predictive nature of the algorithm leads to a minimized number of clutching processes compared to previous work and thereby contributes to increased comfort and minimized component wear. Overall, an average reduction of up to 25% in the electric machine losses can be achieved for the ARTEMIS driving cycles. At the same time, a reduction of the clutching operations by 70% is possible due to the forecast, compared to algorithms only considering the momentary state.

The HVAC system is considered as the largest auxiliary power load in electric vehicles (EV). Therefore, this paper presents a detailed modeling of an EV-based HVAC system to support a priori prediction of HVAC system energy consumption under consideration of the EV users thermal comfort. This prediction is integrated into a navigation system to allow the driver entering the preferred parameters of thermal comfort and advising the driver about the predicted overall energy consumption. The advice acceptance might increase the awareness of the driver regarding the potential saved energy and leads to an energy-efficient vehicle operation by extending the overall driving range.

To support the reliability assessment of safety-relevant distributed automotive systems and reduce its complexity, this paper presents a novel approach that extends virtual prototyping towards error effect simulation. Besides the common functional and timed system simulation, error injection is used to stress error tolerance mechanisms. A quantitative assessment of the overall system reliability is performed by observing the system reactions and identifying incorrect system behavior. To foster the industrial application, the analysis is integrated in a model-based design flow, starting at the modeling level to assemble and parameterize the virtual prototype and to configure the analysis. The feasibility of the proposed approach is demonstrated by analyzing a representative safety-relevant automotive use case.

In this paper we present a novel approach for mapping interconnected software components onto cores of homogenous MPSoC architectures. The analytic mapping process considers shared memory communication as well as the routing algorithm controlling packet-based communication. The software components are mapped with the constraints of avoiding communication conflicts as well as access conflicts to shared memory resources. The core of the elaborated approach consists of an algorithm for software mapping which is inspired by force-directed scheduling from high-level synthesis. Experimental results show that the presented approach increases the overall system performance by 22% while reducing the average communication latency by 35%. For presenting the major advantages of the developed solution, we optimized an advanced driver assistance system on the Tilera TILEPro64 processor.

FPGA circuit implementation is a unidirectional and time-consuming process. Existing approaches like the incremental synthesis try to shorten it, but still need to execute the whole flow for a changed circuit partition. Other approaches circumvent process stages by providing bidirectional mappings between their results. In this paper we propose an approach to provide a bidirectional link between an FPGA design and its HDL code. This link enables the circumvention of the most time-consuming stages (synthesis, mapping, placing, routing) of the FPGA circuit implementation. We implemented our approach in a Java-based EDA tool library, called Static Mapping Library (StML). We demonstrate its applicability by means of hardware debugging and an RTL-based injection of permanent faults, built on top of the StML. Experimental results illustrate that a mapping coverage between 98.5%-100.0% can be obtained, which substantiates the feasibility of this approach. Further experiments illustrate a controllable tradeoff between area overhead, circuit granularity and mapping granularity. With the finest mapping granularity, the area overhead has been between 1.8% and 60.2% for RTL-based circuits. The speedup of the proposed fault injection method has been estimated to be up to 6x for the tested circuits.

This document proposes a new strategy for decelerating a battery electric vehicle from an initial velocity to a final velocity with optimized recuperation of kinetic excess energy. Thereby, we demonstrate a possibility to increase the efficiency - and hence range - without altering the powertrain. The algorithm is implemented in an advanced driver assistance system to guide the driver and - given he accepts the hints - leads to an energy-optimized deceleration trajectory. A situation-adaptive online estimation of influencing parameters, which are not measurable during the drive, is presented. The knowledge of these parameters allows an accurate operation of the proposed functionality. Simulations show an increased energy regeneration of up to 34% for an exemplary vehicle and typical road segments.

This paper briefly describes the latest achievements of a new functional vehicle system to overcome the range anxiety problem of Fully Electric Vehicles (FEV). This is primarily achieved by integrated control and operation strategies to optimize the driving range. The main focus of these control strategies is cooperated electric drivetrain and regenerative braking system. The diverse source of information with on-board and off-board sensors, including navigation system, satellite information, car-to-car, car-to-infrastructure communication and radar and camera systems are primarily utilized to maximize the energy efficiency and correspondingly the range of the FEV.

This paper presents a hybrid cache analysis for the simulation-based evaluation of data caches in embedded systems. The proposed technique uses static analyses at the machine code level to obtain information about the control flow of a program and the memory accesses contained in it. Using the result of these analyses, a high-speed source-level simulation model is generated from the source code of the application, enabling a fast and accurate evaluation of its data cache behavior. As memory accesses are obtained from the binary-level control flow, which is simulated in parallel to the original functionality of the software, even complex compiler optimizations can be modeled accurately. Experimental results show that the presented source-level approach estimates the cache behavior of a program within the same level of accuracy as established techniques working at the machine code level.

Synchronous dataflow (SDF) models are gaining increased attention in designing software-intensive embedded systems. Especially in the signal processing and multimedia domain, dataflow-oriented models of computation are commonly used by designers reflecting the regular structure of algorithms and providing an intuitive way to specify both sequential and concurrent system functionality. Furthermore, dataflow-oriented models are qualified for capturing dynamic behavior due to data-dependent execution. In this work, we extend those data-dependent dataflow models to include dynamic power management (DPM) aspects of a target platform while still meeting hard timing requirements. We capture different system states in a multi-domain scenario approach and develop a state space based on this SDF representation for system analysis and optimization. By traversing the state space of the power-aware scenario modeling we derive a power management configuration with minimized energy dissipation depending on dynamic system behavior.

In this paper, we present a novel approach for automated mapping of software processes onto the cores of MPSoC architectures using a regular packet-based communication infrastructure. During the mapping determination, the communication distance as well as the routing algorithm for packet-based communication are taken into account. The basic idea of the developed approach is the reduction of communication conflicts on the communication network links for reducing the overall communication latency and hence for increasing the total system performance. The presented approach is based on the idea of force-directed scheduling (FDS) from high-level synthesis and uses forces for determining an optimized process mapping. The approach constrains the cores, that are used for the calculation of possible mappings, by the communication distance of the communicating processes. We present results obtained from an advanced driver assistance system on a Tilera TILEPro64 processor.

When migrating to future technology nodes, dependability becomes a major design problem as variability, aging and susceptibility to soft errors increase. The purpose of this program is to research cross-layer solutions that address the physical problems at system-level i.e. at hardware-level, operating system level, application level etc. The goals and an overview of the DFG SPP 1500 research program are presented.

This paper presents an approach for accurately estimating the execution time of parallel software components in complex embedded systems. Timing annotations obtained from highly optimized binary code are added to the source code of software components which is then integrated into a SystemC transaction-level simulation. This approach allows a fast evaluation of software execution times while being as accurate as conventional instruction set simulators. By simulating binary-level control flow in parallel to the original functionality of the software, even compiler optimizations heavily modifying the structure of the generated code can be modeled accurately. Experimental results show that the presented method produces timing estimates within the same level of accuracy as an established commercial tool for cycle-accurate instruction set simulation while being at least 20 times faster.

This work presents a SystemC-based simulation approach for fast performance analysis of parallel software components, using source code annotated with low-level timing properties. In contrast to other source-level approaches for performance analysis, timing attributes obtained from binary code can be annotated even if compiler optimizations are used without requiring changes in the compiler. To consider concurrent accesses to shared resources like caches accurately during a source-level simulation, an extension of the SystemC TLM-2.0 standard for reducing the necessary synchronization overhead is proposed as well. This enables the simulation of low-level timing effects without performing a full-fledged instruction set simulation and at speeds close to pure native execution.

Design and specification errors are hard to find in the traditional automotive system design flow. Consequently, these errors may be detected very late e.g. in a hardware prototype or even worse in the final product. In order to allow the verification of distributed embedded systems in early design phases, this work proposes a flexible and efficient virtual prototyping approach in order to check the consistency of system specifications. Our virtual prototyping approach has been applied to the Media Oriented Systems Transport (MOST) specification revision 3.0 and verifies the influence of two newly specified algorithms, namely Ring Break Diagnosis and Sudden Signal Off detection, with respect to numerous network configurations. In total we have verified the specification using more than 105automatically generated network configurations. The overall costs for network modelling and verification compared to cost-expensive error detection and correction at later design phases have been significantly reduced.

This paper describes the design of an automotive traffic sign recognition application. All stages of the design process, starting on system-level with an abstract, pure functional model down to final hardware/software implementations on an FPGA, are shown. The proposed design flow tackles existing bottlenecks of today's system-level design processes, following an early model-based performance evaluation and analysis strategy, which takes into account hardware, software and real-time operating system aspects. The experiments with the traffic sign recognition application show, that the developed mechanisms are able to identify appropriate system configurations and to provide a seamless link into the underlying implementation flows.

In this paper, we show how to prune the population size of the Learning Classifier System XCS for complex problems. We say a problem is complex, when the number of specified bits of the optimal start classifiers (the problem dimension) is not constant. First, we derive how to estimate an equivalent problem dimension for complex problems based on the optimal start classifiers. With the equivalent problem dimension, we calculate the optimal maximum population size just like for regular problems, which has already been done. We empirically validate our results. Furthermore, we introduce a subsumption method to reduce the number of classifiers. In contrast to existing methods, we subsume the classifiers after the learning process, so subsuming does not hinder the evolution of optimal classifiers, which has been reported previously. After subsumption, the number of classifiers drops to about the order of magnitude of the optimal classifiers while the correctness rate nearly stays constant.

In this paper, a novel approach for integrating static non-preemptive software scheduling in formal bottom-up performance evaluation of embedded system models is described. The presented analysis methodology uses a functional SystemC implementation of communicating processes as input. Necessary model extensions towards capturing of static non-preemptive scheduling are introduced and the integration of the software scheduling in the formal analysis process is explained. The applicability of the approach in an automated design flow is presented using a SystemC model of a JPEG encoder.

In this paper, we present a novel framework for the automated generation of Network-on-Chips (NoC) architectures, that enables architecture exploration and optimization. The automated generation of Network-on-Chip architectures covers beside the generation of the communication infrastructure, the automated integration of IP-components. The automated integration of IP-components is based on IP-XACT interface descriptions of these components. In this paper, we show the integration of components into the Network-on-Chip architecture exemplarily for the SimpleScalar Instruction-Set-Simulator (ISS). The Network-on-Chip architecture used in this paper, is based on a parametrizable switch implemented as Transaction-Level-Model (TLM) in SystemC. The Transaction-Level-Model of the switch provides the possibility of integrating different routing algorithms like deterministic or adaptive routing algorithms. Different Network-on-Chip architectures like mesh-, torus-, and hypercube-topologies can be generated, based on this switch. The proposed framework can be used for exploration and optimization of Network-on-Chip architectures, by comparing Network-on-Chip architectures with different topologies and routing algorithms.

This paper presents an approach for cycle-accurate simulation of embedded software by integration in an abstract SystemC model. Compared to existing simulation-based approaches, we present a hybrid method that resolves performance issues by combining the advantages of simulation-based and analytical approaches. In a first step, cycle-accurate static execution time analysis is applied at each basic block of a cross-compiled binary program using static pro-cessor models. After that, the determined timing information is back-annotated into SystemC for fast simulation of all effects that can not be resolved statically. This allows the consideration of data dependencies during run-time and the incorporation of branch pre-diction and cache models by efficient source code instrumentation. The major benefit of our approach is that the generated code can be executed very efficiently on the simulation host with approxi-mately 90 % of the speed of the untimed software without any code instrumentation.

In this paper, a novel design and analysis methodology for simulation-based determination of non-functional properties of a system design, like performance, power consumption and temperature is proposed. For simulation acceleration and handling of complexity issues, the design flow includes automated abstraction of component functionality. Specified platform attributes as dynamic power management and formally declared temporal input stimuli are automatically transformed to non-functional SystemC models. The framework implements the ability for automated online and offline analysis of non-functional system-on-chip properties.

In this paper, we propose an approach for modeling distributed embedded systems in a holistic way starting from an abstract specification of system requirements. We use the unified modeling language (UML), which is very popular in software modeling and development, for describing both the target platform and the functionality, which has to be performed on that target platform, at a high abstraction level - even at system level. Therefore, we extended the existing UML profile MARTE to meet the requirements of distributed systems. These extensions enable to associate the elements of the model semantically and hence to use UML as a common underlying data model for system representation. Based on the holistic modeling approach an executable simulation model is generated in SystemC to facilitate exploration and verification of system behavior.

In this paper, we present an approach for control-flow aware communication and conflict analysis of systems of parallel communicating processes. This approach allows to determine the global timing behavior of such a system and to detect communication that might produce conflicts on shared communication resources. Furthermore, we show the incorporation of temporal environment models in order to analyze their influence on the system behavior. Based on the determined conflicts, an automated allocation and binding approach for shared resources to resolve potential access conflicts is proposed. All analysis steps can be performed starting with a TLM SystemC model of the entire system without any need for user interaction. Finally, a SystemC model of a Viterbi decoder is used as case study to demonstrate the capability of our approach.

AUTOSAR is a recent specification initiative which focuses on a model-driven architecture like methodology for automotive applications. However, needed engineering steps, or how-to-come from a logical to a technical architecture respectively implementation, are not well supported by tools, yet. In contrast, SystemC offers a comprehensive way to simulate, analyze, and verify software. Furthermore, it is even able to take the timing behavior of underlying hardware and communication paths into account. Already at a first glance, there are many similarities with respect to the modeling structure between the both concepts. Therefore, this paper discusses approaches on how to use SystemC during the design process of AUTOSAR-conform systems

In this paper, we present a novel fully adaptive and fault-tolerant routing algorithm for Network-on-Chips (NoCs) called Force-Directed Wormhole Routing (FDWR). The proposed routing algorithm is implemented in the switches of a TLM (Transaction Level Model) packet switching NoC using SystemC. Based on these switches, mesh, torus, and hypercube topologies for NoCs can be automatically generated. We show how the proposed algorithm distributes the traffic uniformly across the entire network to avoid overloaded links. Simulation results depict that the proposed routing algorithm is able to route packets even in the case of faulty links or switches in the NoC. Furthermore, it is shown that in the case of faulty switches the area around that switches is not overloaded and that the traffic is uniformly distributed across the entire network.

In this paper we present a generic interconnect fabric for transaction level modelling tackeling three major aspects. First, a review of the bus and IO structures that we have analysed, which are common in todays system on chip environments, and require to be modelled at a transaction level. Second our findings in terms of the data structures and interface API's that are required in order to model those (and we believe other) busses and IO structures. Third the surrounding infrastructure that we believe can, and should be in place to support the modelling of those busses and IO structures. We will present the infrastructure that we have built, and indicate where our future work will hea.

UML2 and SysML try to adopt techniques known from software development to systems engineering. However, the focus has been put on modeling aspects until now and quantitative performance analysis is not adequately taken into account in early design stages of the system. In this paper, we present our approach for formal and simulation based performance analysis of systems specified with UML2/SysML. The basis of our analysis approach is the detection of communication that synchronize the control flow of the corresponding instances of the system and make the relationship explicit. Using this knowledge, we are able to determine a global timing behavior and violations of this effected by preset constraints. Hence, it is also possible to detect potential conflicts on shared communication resources if a specification of the target architecture is given. With these information it is possible to evaluate system models at an early design stage

The evolution of CMOS technologies leads to integrated circuits with ever smaller device sizes, lower supply voltage, higher clock frequency and more process variability. Intermittent faults effecting logic and timing are becoming a major challenge for future integrated circuit designs. This paper presents an organic computing inspired SoC architecture which applies self-organization and self-calibration concepts to build reliable SoCs with lower overheads and a broader fault coverage than classical fault-tolerance techniques. We demonstrate the feasibility of this approach by example on the processing pipeline of a public-domain RISC CPU core

The application of a cycle accurate binary translator for rapid prototyping of SoCs is presented. This translator generates code to run on a rapid prototyping system consisting of a VLIW processor and FPGAs. The generated code is annotated with information that triggers cycle generation for the hardware in parallel with the execution of the translated program. The VLIW processor executes the translated program whereas the FPGAs contain the hardware for the parallel cycle generation and the bits interface that adapts the bits of the VLIW processor to the SoC bits of the emulated processor core.

In this paper we present an approach for analysis of systems of parallel, communicating processes for SoC design. We present a method to detect communications that synchronize the program flow of two or more processes. These synchronization points set the processes into relation and allow the determination of the global timing behavior of such a system. Using the results of our method for communication analysis, we present a new method to detect communications that might produce conflicts on shared communication resources. This information can be used for the assignment of communication resources.

This paper presents a new approach on combined high-level synthesis and partitioning for FPGA-based multi-chip emulation systems. The goal is to synthesize a prototype with maximal performance under the given area and interconnection constraints of the target architecture. Interconnection resources are handled similarly to functional resources, enabling the scheduling and the sharing of inter-chip connections according to their delay. Moreover, data transfer serialization is performed completely or partially, depending on the mobility of the data transfers, in order to satisfy the given interconnection constraints. In contrast to conventional partitioning approaches, the constraints of the target architecture are fulfilled by construction.

This paper presents a new approach to cross-level hierarchical high-level synthesis. A methodology is presented, that supports the efficient synthesis of hierarchical specified systems while preserving the hierarchical structure. After synthesis of each subsystem, the determined component schedule and the synthesized RT-structure are added to its algorithmic specification. This provides an automatic selection of optimized complex components. Furthermore, the component schedule enables the sharing of unused subcomponents across different hierarchical levels of the design.

This paper presents a new approach to hierarchical high-level synthesis with respect to internal register-transfer structures of complex components. Entire subdesigns can efficiently be used as complex components at a higher hierarchical level of the design. After synthesis, the calculated schedule of each subdesign is added to its register-transfer component model. This enables the sharing of unused subcomponents across different hierarchical levels of the design. Especially, subcomponents of autonomous components, with a separate controller can also be shared. As a result, the presented methodology offers a high degree of optimization to hierarchically specified designs.