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Peivand Tehrani

dblp:06/7450 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 2009
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 81% Integrated circuit design · 19%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation
timing analysis
0.112009
Worst-case aggressor-victim alignment with current-source driver models · DAC 2009
Integrated circuit design
digital circuit design
0.012009
Worst-case aggressor-victim alignment with current-source driver models · DAC 2009
Electronic design automation › hardware verification and test
static noise analysis
0.012009
Worst-case aggressor-victim alignment with current-source driver models · DAC 2009

Methods — techniques the papers use, named apart from their topics

heuristic optimization · 0.1HSPICE simulation · 0.1
YearPublicationVenuePosition
2009 Worst-case aggressor-victim alignment with current-source driver models
abstract
Crosstalk delay-noise which occurs due to the simultaneous transitions of victim and aggressor drivers is very sensitive to their mutual alignment. Hence, during static noise analysis, it is crucial to identify the worst-case victim-aggressor alignment which results in the maximum delay-noise. Although several approaches have been proposed to obtain the worst-case aggressor alignment, most of them compute only the worst-case stage delay of the victim. However, in reality it is essential to compute the worst-case combined delay of victim stage and victim receiver gate [5, 9]. We propose a heuristic approach to compute the worst-case aggressor alignment which maximizes the victim receiver output arrival time. In this work, we use a novel cumulative gate overdrive voltage (CGOV ) metric to model the victim receiver output transition. HSPICE simulations, performed on industrial nets to validate the proposed methodology, show an average error of 1.7% in delay-noise when compared to the worst-case alignment obtained by an exhaustive sweeping.
Ravikishore Gandikota, Li Ding 0002, Peivand Tehrani, David T. Blaauw
DAC3